Transistor device comprising an asymmetric embedded semiconductor alloy
AssigneeGlobalfoundries Inc.
InventorsVassilios Papageorgiou, Jan Hoentschel, Robert Mulfinger, Casey Scott
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Abstract
Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.
Claims23
A method, comprising:
- forming a first cavity in a semiconductor region having formed thereon a gate electrode structure, said first cavity located laterally adjacent to a first sidewall of said gate electrode structure;
- forming a second cavity in said semiconductor region laterally adjacent to a second sidewall of said gate electrode structure, said first and second sidewalls being positioned oppositely to each other, said first and second cavities differing in at least one of a depth and a width;
- forming a semiconductor alloy in said first and second cavities, said semiconductor alloy inducing strain in a channel region positioned in said semiconductor region below said gate electrode structure;
- and
- removing a portion of said semiconductor alloy adjacent to one of said first sidewall and said second sidewall.
A method of forming an embedded semiconductor material in a transistor, the method comprising:
- introducing an implantation species into a semiconductor region by performing a tilted implantation process, wherein said semiconductor region has formed thereon a gate electrode structure comprising first and second sidewalls, and wherein a dose of said implantation species in said semiconductor region is higher adjacent to said first sidewall than adjacent to said second sidewall;
- forming a first cavity and a second cavity in said semiconductor region in a common etch process by using said implantation species as an etch control species, wherein said first and second cavities are positioned on opposite sides of said gate electrode structure and adjacent to said first and second sidewalls, respectively, and wherein a depth of said first cavity is less than a depth of said second cavity;
- and
- forming a semiconductor material in said first and second cavities.
A method, comprising:
- forming a gate electrode structure above an active region of a semiconductor device, said active region have a first area portion of a first side of said gate electrode structure and a second area portion on a second side of said gate electrode structure;
- modifying an etch behavior of material comprising said active region in said first area portion only;
- forming a first cavity having a first depth and a first width in said first area portion;
- forming a second cavity having a second depth and a second width in said second area portion, wherein said first and second cavities are formed during a common etch process, and wherein at least one of said first depth and said first width is different than at least a respective one of said second depth and said second width;
- and
- forming a semiconductor alloy in said first and second cavities, wherein said semiconductor alloy is adapted to induce a strain in a channel region positioned in said active region below said gate electrode structure.
Dependencies are inferred from the claim text.