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US 8,138,039 B2Granted
Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
AssigneeMicron Technology, Inc.
InventorsSanh D. Tang, Robert J. Burke, Anand Srinivasan
Life of this patent
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Abstract
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
Claims18
A method of fabricating a vertical semiconductor transistor, said method comprises:
- providing a semiconductor substrate;
- forming a polysilicon pillar on the substrate;
- using the thickness of a first film layer to define a first source/drain region of the transistor as the top portion of the pillar;
- forming a spacer layer around the top portion of the pillar;
- using the thickness of a second film layer to define a channel region of the transistor as the central portion of the pillar and to align a transistor gate with the channel region of the transistor;
- depositing a dielectric layer on the pillar in alignment with the channel region of the transistor;
- forming the transistor gate in alignment with the channel region of the transistor, wherein the transistor gate is formed to surround the pillar with the dielectric layer between a conductive material and the pillar;
- using the thickness of the spacer layer around the top portion of the pillar to define the thickness of the transistor gate, a top portion of the transistor gate being underneath a bottom portion of the spacer layer;
- and
- defining a second source/drain region of the transistor as the bottom portion of the pillar using the thickness of a third film layer.
7 more elements
A method of fabricating a semiconductor structure containing at least one vertical transistor, the method comprising the acts of:
- providing a substrate wherein at least a portion of the working surface thereof is polysilicon;
- depositing first, second and third material layers on the substrate;
- forming at least one hole through the material layers over the polysilicon portion of the substrate surface to thereby expose the polysilicon;
- epitaxially growing a respective polysilicon pillar from the polysilicon portion of the substrate surface through each of the at least one hole;
- forming a protective cap layer over each pillar;
- removing the third material layer to thereby expose the sidewall surface of a top portion of each pillar;
- forming a spacer layer around the top portion of each pillar on the exposed sidewall surface thereof;
- removing the second material layer to thereby expose the sidewall surface of a central portion of each pillar, the central portion being adjacent and beneath the spacer layer;
- depositing a dielectric layer around the central portion of each pillar on the exposed sidewall surface thereof;
- and
- surrounding the dielectric layer of each pillar with a layer of conductive material.
8 more elements
A method of fabricating a semiconductor structure containing at least one vertical transistor, the method comprising the steps of:
- providing a substrate having a silicon layer disposed over an insulator layer;
- patterning the silicon layer to form M digit lines, wherein M is a positive integer;
- depositing a plurality of material layers over the substrate;
- forming an M×N array of holes aligned over the M digit lines, wherein N is a positive integer and N holes are formed along each digit line and are aligned with the holes formed over adjacent digit lines;
- epitaxially growing a respective polysilicon pillar from the polysilicon portion of the substrate surface through each hole;
- forming a protective cap layer over each pillar;
- exposing a sidewall surface of a top portion of each pillar;
- forming a spacer layer around the top portion of each pillar on the exposed sidewall surface;
- exposing the sidewall surface of a central portion of each pillar;
- depositing a dielectric layer around the central portion of each pillar on the exposed sidewall surface;
- and
- surrounding the dielectric layer of each pillar with a layer of conductive material.
9 more elements
Dependencies are inferred from the claim text.