Method and structure for gate height scaling with high-k/metal gate technology
AssigneeInternational Business Machines Corporation
InventorsMichael P. Chudzik, Ricardo A. Donaton, William K. Henson, Yue Liang
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Abstract
A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
Claims16
A method of forming a semiconductor structure, comprising:
- forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor;
- selectively removing the dummy gate while protecting the at least one polysilicon feature;
- and
- forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
A method of forming a semiconductor device, comprising:
- forming a high-k dielectric layer on a substrate;
- forming a metal layer on the high-k dielectric layer;
- forming a silicon layer on the metal layer;
- forming an etch-stop layer on the silicon layer;
- forming a polysilicon layer on the etch-stop layer;
- patterning the polysilicon layer into a dummy gate associated with a transistor and at least one polysilicon feature associated with at least one other device;
- forming a barrier layer over the substrate, the dummy gate, and the at least one polysilicon feature;
- removing a portion of the barrier layer from over the dummy gate while masking the barrier layer over the at least one polysilicon feature;
- selectively removing the dummy gate to expose a portion of the etch-stop layer;
- removing the exposed portion of the etch-stop layer to expose a portion of the silicon layer;
- and
- forming a silicide gate contact from the exposed silicon layer.
Dependencies are inferred from the claim text.