Method for manufacturing a phase change memory device with pillar bottom electrode

A method for manufacturing a plurality of memory cells, comprising:

• providing a substrate including access circuitry for the plurality of memory cells, and having a contact surface with an array of conductive contact plugs connected to the access circuitry;
• adding a layer of bottom electrode material on the contact surface of the contact plugs of the substrate;
• forming electrode pillar masks only partly covering the bottom electrode material, and isotropically trimming electrode pillar masks on the layer of bottom electrode material;
• removing material of the layer of bottom electrode material to form a pattern of electrode pillars on corresponding conductive contact plugs in the array of conductive contact plugs, wherein the electrode pillars have respective bottom surfaces in electrical connection with corresponding conductive contact plugs in the array of conductive contact plugs;
• forming a layer of dielectric diffusion barrier material covering the electrode pillars in the pattern of electrode pillars and the contact surface;
• planarizing layer of dielectric diffusion barrier material and electrode pillars to provide a bottom electrode layer having a thickness less than about 120 nm with an electrode surface exposing top surfaces of the electrode pillars in the pattern of electrode pillars, so that the respective top surfaces of the electrode pillars in the pattern of pillars have areas less than about 2000 nm2 and are substantially uniform over the pattern of pillars;
• forming a layer of programmable resistive material on the electrode surface, the programmable resistive material comprising a phase change material having a thickness less than about 120 nm;
• forming a layer of top electrode material over the layer of programmable resistive material;
• and
• patterning the layer of programmable resistive material and the layer of top electrode material at a same time.

A method for manufacturing a plurality of memory cells, comprising:

• providing a substrate including access circuitry for the plurality of memory cells, and having a contact surface with an array of conductive contact plugs connected to the access circuitry;
• adding a layer of bottom electrode material comprising a compound or alloy including a metal and nitrogen on the contact surface of the contact plugs of the substrate;
• forming a mask on the layer of bottom electrode material defining a pattern of spots, including lithographically defining a lithographic pattern including etch mask patches over the conductive contact plugs in the array of conductive contact plugs, and isotropically trimming the etch mask patches to produce a pattern of spots having sub-lithographic dimensions;
• removing material of the layer of bottom electrode material according to the pattern of spots to form a pattern of electrode pillars on corresponding conductive contact plugs in the array of conductive contact plugs, wherein the electrode pillars have respective bottom surfaces in electrical connection with corresponding conductive contact plugs in the array of conductive contact plugs;
• forming a layer of dielectric diffusion barrier material comprising a compound including silicon and nitrogen covering the electrode pillars in the pattern of electrode pillars and the contact surface;
• planarizing layer of dielectric diffusion barrier material and electrode pillars to provide a bottom electrode layer with an electrode surface exposing top surfaces of the electrode pillars in the pattern of electrode pillars, so that the respective top surfaces of the electrode pillars in the pattern of pillars have areas less than about 2000 nm2 and are substantially uniform over the pattern of pillars;
• during said planarizing, monitoring thickness of the dielectric layer, and stopping the planarizing upon detection of a predetermined thickness less than about 120 nm;
• forming a layer of chalcogenide on the electrode surface having a thickness less than about 120 nm;
• forming a layer of top electrode material over the layer of programmable resistive material;
• and
• forming pads comprising portions of the layer of phase change material and of the layer of top electrode material patterned at a same time as the layer of phase change material, for individual memory cells,
• applying a layer of dielectric fill material over the pads,
• forming via contacts through the layer of dielectric fill material, and
• forming a patterned conductor layer including bit lines in electrical communication with the via contacts.