Wafer level integrated interconnect decal and manufacturing method thereof
AssigneeInternational Business Machines Corporation
InventorsPeter A. Gruber, Jae-Woong Nah
Life of this patent
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Abstract
A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.
Claims25
A method of producing wafer level interconnect decals, said method comprising the steps of:
- (a) providing a plurality of superimposed apertured decals, said plurality of decals including an upper layer having tapered feature holes, a center layer having through features holes in alignment with said tapered feature holes in alignment with the through feature holes in a bottom layer located on an opposite side of said center layer;
- (b) forming vacuum holes in said center layer in alignment with vacuum holes in said bottom layer arranged about the peripheries of said layers for maintaining said layers in aligned relationship;
- (c) positioning a carrier beneath said bottom layer, said carrier having vacuum holes located in alignment with the vacuum holes in said bottom and center layers;
- (d) imparting a vacuum to said vacuum holes to maintain said carrier and decal layers in a clamped position;
- (e) filling the feature holes in said decal layers with molten solder and cooling said solder;
- (f) peeling said upper layer from said center layer and applying an adhesive layer to the exposed surface of said center layer encompassing projecting solder portions;
- and
- (g) mounting a wafer on said exposed surface in contact with said adhesive and solder portions.
A wafer level interconnect decal arrangement, comprising:
- (a) a plurality of superimposed apertured decals, said plurality of decals including an upper layer having tapered feature holes, a center layer having through features holes in alignment with said tapered feature holes in alignment with the through feature holes in a bottom layer located on an opposite side of said center layer;
- (b) vacuum holes in said center layer being in alignment with vacuum holes in said bottom layer arranged about the peripheries of said layers for maintaining said layers in aligned relationship;
- (c) a carrier being positioned beneath said bottom layer, said carrier having vacuum holes located in alignment with the vacuum holes in said bottom and center layers;
- whereby a vacuum is imparted to said vacuum holes to maintain said carrier and decal layers in a clamped position;
- (d) the feature holes in said decal layers being filled with molten solder and cooled;
- (e) said upper layer being peeled from said center layer, and an adhesive layer applied to the exposed surface of said center layer encompassing projecting solder portions;
- and
- (f) a wafer being mounted on said exposed surface in contact with said adhesive and solder portions.
Dependencies are inferred from the claim text.