# US 8,136,237 B2 · Method of interconnecting electronic wafers

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- Number: US 8,136,237 B2
- Document ID: US8136237B2
- Status: Granted
- Kind: B2
- Application number: 12/522,426
- Filed: 2008-01-28
- Published: 2010-11-04
- Granted: 2012-03-20
- Earliest claimed: 2007-01-30
- Assignees: 3D Plus
- Inventors: Christian Val
- Web page: https://patentgrep.com/patent/US8136237B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10W 72/072: {of bump connectors}
- H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser}
- H10W 72/07254: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- Y10T 29/49126: Assembling bases
- Y10T 29/49165: by forming conductive walled aperture in base
- Y10T 29/49167: with deforming of conductive path
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

## Claims

### Claim 1

A method of interconnecting electronic components of a first wafer with electronic components of a second wafer, each wafer having metallized vias which pass through the wafer in a thickness direction of said wafer, said method comprising the following steps:
depositing a drop of conductive ink containing solvents on each of the metallized vias of the first wafer;
stacking the second wafer on the first wafer so that the vias of the second wafer are substantially superposed on the vias of the first wafer;
removing 50 to 90% of the solvents contained in the drops between the first and second wafers by heating or applying a vacuum, so as to obtain a pasty ink; and
laser sintering the pasty ink drops so as to produce electrical connections between the superposed metallized vias.

### Claim 2 (depends on 1)

The method as claimed in claim 1, further comprising checking at least said one electrical connection by means of an integrated laser diode.

### Claim 3 (depends on 1)

The method as claimed in claim 1, further comprising connecting the first wafer beforehand to at least one other wafer.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the conductive ink comprises nanoparticles of a metal including Ag or Cu or Au.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the drops are deposited by an ink jet or by screen printing.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein the metallized vias have metal which fills the vias and thus forms pillars.

### Claim 7 (depends on 6)

The method as claimed in claim 6, wherein one of said pillars is extended by a protuberance.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein,
said first or second wafer has two faces,
an electrically conductive collar surrounds the respective metallized via on said one or both faces of flail said wafer, and
the drop deposited on the via is in contact with said electrically conductive collar.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein the collar forms a full disk largely centered on the via.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein at least one collar is provided with bumps.