Method and apparatus for synthesizing hardware counters from performance sampling

#1. Field of the Invention

#This invention relates to computing systems and more specifically to observing and optimizing costs of various system events through data space profiling.

#2. Description of the Relevant Art

#FIG. 1 illustrates a method for performing data space profiling, according to one embodiment.

#FIGS. 2A and 2B are block diagrams illustrating annotation of code to associate instruction instances with language constructs of source-level data objects, according to various embodiments.

#FIG. 3 is a flow chart illustrating a method for attributing sampled runtime events to source-level data object language constructs, according to one embodiment.

#While the invention is described herein by way of example for several embodiments and illustrative drawings, those skilled in the art will recognize that the invention is not limited to the embodiments or drawings described. It should be understood, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to.

#Modern computer systems are using increasing numbers of ever-faster processors to solve larger and larger problems. However, performance of those processors may be limited by the need to supply data to them at ever increasing rates. In some systems, a hierarchy of caches between the processors and main memory may be used to improve performance. In these systems, the processors may run at full speed when using data from the caches closest to the processors, but may be frequently stalled loading data from or storing data to the primary caches through secondary or tertiary caches and, ultimately, to or from main memory. Understanding how an application's data is structured in memory and how it passes from memory through the cache hierarchy may facilitate understanding and improving the performance of applications on these systems.

#The data space profiler described herein may provide per-instruction details of memory accesses in the annotated disassembly, and may provide data aggregated and sorted by object structure types and elements, in some embodiments. This may in some embodiments provide a new observability perspective for application developers. For example, the underlying framework of the profiler may provide a system and method for providing cache miss data to compilers and dynamic code generators, thus allowing cache-related application optimizations. The system and method may be applied to profiling data related to other types of runtime events, or execution hindrances, in some embodiments.