Method for testing integrated circuits

A method comprising:

• a processor of a computer generating a test netlist, said test netlist describing nets of a circuit and faults for testing said nets;
• generating a physical netlist, said physical netlist describing quantitative, geometric or parametric features of said nets;
• selecting a set of quantitative, geometric or parametric features of nets of said circuit from said physical netlist, said circuit having one or more pattern input points and one or more pattern observation points connected by said nets, each of said nets defined by an input point and all fan out paths to (i) input points of other nets of said nets or (ii) to said pattern observation points, each net of said nets comprising one or more connected segments;
• selecting a unit of measure for each feature of said set of features;
• assigning a weight to each said segment of each fan out path of each of said nets based on a number of said unit of measure of said feature in each segment of each fan out path of each of said nets;
• generating a weighted test netlist by mapping said weights of each said segment from said physical netlist to corresponding faults in said test netlist, said faults being independent of any particular fault model;
• said processor generating a set of test patterns based on said weighted test netlist.