Apparatus and computer program product for semiconductor yield estimation

A computer program product executed on a computer system and comprising a computer usable device having computer usable program code for performing critical area analysis on an integrated circuit design having redundant and non-redundant elements, the computer usable program code comprising:

• computer usable program code for generating a graphical data symbol representation of the integrated circuit design;
• computer usable program code for identifying any redundant elements of the integrated circuit in the graphical data symbol representation with unique identifiers;
• and
• computer usable program code for analyzing the graphical data symbol representation for undesired open-causing defects in wires and/or vias for the non-redundant elements,
• wherein the computer usable program code treats redundant and non-redundant elements differently during yield estimations in performing the critical area analysis, and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design, and
• wherein the generating comprises generating graphical design data (GDD) shapes for performing the critical area analysis for short defects and opens, wherein the critical area analysis for short defects uses the GDD and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design, and wherein the critical area analysis for the opens uses the GDD and performs the critical area analysis for only the non-redundant elements of the integrated circuit design.

An apparatus for performing critical area analysis on an integrated circuit design having redundant and non-redundant elements, the apparatus comprising:

• a system for generating a graphical data symbol representation of the integrated circuit design;
• a system for identifying any redundant elements of the integrated circuit in the graphical data symbol representation with unique identifiers;
• a system for analyzing the graphical data symbol representation for undesired open-causing defects in wires and/or vias for the non-redundant elements,
• wherein the apparatus treats redundant and non-redundant elements differently during yield estimations in performing the critical area analysis, and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design, and
• wherein the generating comprises generating graphical design data (GDD) shapes for performing the critical area analysis for short defects and opens, wherein the critical area analysis for short defects uses the GDD and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design, and wherein the critical area analysis for the opens uses the GDD and performs the critical area analysis for only the non-redundant elements of the integrated circuit design.