US 8,136,065 B2Granted

Integrated prototyping system for validating an electronic system design

AssigneeINPA Systems, Inc.

InventorsThomas B. Huang, Chioumin M. Chang

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Abstract

An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.

Claims29

Dependent claims

An integrated prototyping system (IPS) for a user to verify and validate an electronic system design (ESD) with design data provided as a plurality of hierarchical design elements HDEs each having its corresponding test bench and said HDEs further interacting with one another according to a pre-defined functional validation specification, said IPS comprising:

a) a reprogrammable logic device (RPLD) having:
an emulation timing base and an RPLD-interface for configuring, programming, controlling and monitoring a number of programmed HDEs under validation on the RPLD while receiving and outputting corresponding streams of exchanging vectors, said RPLD further switchably coupled to a plurality of external peripheral electronic devices (PED);
b) an electronic design automation (EDA) simulator for reading the design data, simulating and then verifying, while receiving and outputting corresponding streams of exchanging vectors, selected members of said HDEs in conjunction with their test benches, said EDA simulator further comprising a simulator interface for controlling said EDA simulator's execution;
and
c) an IPS controller bridging the RPLD and the EDA simulator respectively through the RPLD-interface and the simulator interface, said IPS controller further comprising an IPS executive for progressively verifying and validating the design data by:
c1) partitioning the ESD into a set of validated HDEs and a set of HDE candidates each being not yet verified;
c2) verifying the HDE candidates in the EDA simulator and validating the HDE candidates in said RPLD against said functional validation specification;
and
c3) repeating steps c1) and c2) till all HDE candidates are verified in the EDA simulator and validated in the RPLD against said functional validation specification.

6 more elements

An integrated prototyping system (IPS), comprising:

a logic simulator having a simulator interface for (a) receiving a first set of design elements of an electronic device to be simulated in the logic simulator, (b) receiving test vectors for the design elements under simulation, and (c) providing output vectors from the design elements under simulation;
an emulation system including one or more programmable logic devices having an emulation system interface for (a) allowing a second set of design elements of an electronic device to be configured and emulated in the programmable logic devices, (b) receiving test vectors to be applied to the design elements configured in the programmable logic devices, and (c) providing output vectors from the design elements configured in the programmable logic devices;
and
a controller having access to both the emulation system interface and the simulator interface, wherein the controller progressively verifies and validates the electronic device against a specification by:
(a) partitioning design elements of the electronic device into the first design elements and a set of validated design elements;
(b) (i) providing, over the simulator interface, the first set of design elements and corresponding test vectors to the logic simulator over the simulator interface for simulation and (ii) providing, over the emulation system interface, selected members of the first set of design elements that have been simulated as the second set of design elements, the second set of design elements being provided to be configured in the programmable logic device for emulation using corresponding test vectors;
(c) (i) receiving, over the simulator interface the output vectors of the design elements under simulation, (ii) receiving, over the emulation system interface, the output vectors of the designed elements configured in the programmable logic devices, and (iii) synthesizing next test vectors for the design elements under simulation and for the design elements configured in the programmable logic devices;
and
(d) repeating steps (a)-(c) until the requirements of the specification are satisfied.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/110,233Filed 25 Apr 2008 · continuation in part
Priority: 10 Dec 2007
Published: US 2009/0150838 A111 Jun 2009
Granted: 13 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 2117/08
Details relating to the type or aim of the circuit design: hW-SW co-design, e.g. HW-SW partitioning
G06F
Computing and data processing

Family

Application11/953,366Parent of this continuation-in-part · filed 10 Dec 2007
US 2009/0150839 A1Pre-grant publication · published 11 Jun 2009
US 2009/0150838 A1Published application
US 7,908,576 B2Related patent
US 8,136,065 B2This patent

From the US filing history. Foreign family members aren’t listed.