Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method

#This application claims priority to Korean Patent Application No. 10-2007-0021171, filed on Mar. 2, 2007, the subject matter of which is hereby incorporated by reference in its entirety.

#1. Field of the Invention

#Embodiments of the invention relate to a semiconductor memory device and a related error checking and correction (ECC) method. In particular, embodiments of the invention relate to a multi-layer semiconductor memory device having an ECC engine and a related ECC method performed using a multi-layer semiconductor memory device.

#Embodiments of the invention will be described herein with reference to the accompanying drawings, in which:

#FIG. 1 is a schematic side view of a conventional multi-layer semiconductor memory;

#FIG. 2 is a schematic view of a cell structure of a conventional bi-directional resistive random access memory (RRAM);

#In the drawings, like reference symbols indicate like or similar elements throughout. Hereinafter, embodiments of the invention will be described in the context of a resistive random access memory (RRAM) since RRAM may readily be implemented as a multi-layer semiconductor memory device. In particular, a bi-directional RRAM may be used. However, the invention is not limited to only RRAMs.

#FIGS. 7A through 7D illustrate multi-layer semiconductor memory devices 700a, 700b, 700c, and 700d in accordance with embodiments of the invention. Referring to FIGS. 7A through 7D, each of multi-layer semiconductor memory devices 700a, 700b, 700c, and 700d comprises first through third payload memory cell array layers and a parity memory cell array layer. In addition, each memory cell array layer comprises a memory cell array and, as used herein, storing data to a memory cell array layer means storing the data to the memory cell array that the memory cell array layer comprises. As used herein, a “payload” memory cell array layer is a memory cell array layer in which the multi-layer semiconductor memory device stores payload data, and a “parity” memory cell array layer is a memory cell array layer in which the multi-layer semiconductor memory device stores parity data. Also, as used herein “payload” data refers to any data that is not used as parity data, and a parity memory cell array layer may also be referred to as an “ECC layer”. In the drawings, differential shading is used to distinguish a parity memory cell array layer or a memory region in which parity data is stored from a payload memory cell array layer or a memory region in which payload data is stored. That is, parity memory cell array layers and memory regions in which parity data is stored (“parity regions”) are shaded, while payload memory cell array layers and memory regions in which payload data is stored are not shaded. Additionally, as used herein, one “memory cell array layer” is physically distinct from other memory cell array layers and is disposed in a different plane than other memory cell array layers. Thus, as used herein, first and second memory cell array layers, for example, are physically distinct layers disposed within different planes.

#In each of multi-layer semiconductor memory devices 700a, 700b, 700c, and 700d, payload data is stored in the first through third payload memory cell array layers, and parity data is stored in the parity memory cell array layer, which is a separate layer with respect to the first through third payload memory cell array layers. Although the embodiments illustrated in FIGS. 7A through 7D each comprise four memory cell array layers, a multi-layer semiconductor memory device in accordance with an embodiment of the invention may comprise more than four memory cell array layers.