Non-volatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsHironori Uchikawa, Tatsuyuki Ishikawa, Mitsuaki Honma
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Abstract
A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.
Claims10
A non-volatile semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells arrayed therein, the memory cells being capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage;
- a parity data adder circuit configured to add parity data for error correction to every certain data bits to be stored in the memory cell array;
- a frame converter circuit configured to uniformly divide frame data containing the data bits and the parity data into N pieces of subframe data;
- and
- a programming circuit configured to store the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits,
- wherein the parity data is stored in the N sub-pages in order beginning from a sub-page with the smallest variation in bits between adjacent threshold voltage states.
A non-volatile semiconductor memory device, comprising:
- a parity data adder circuit configured to add parity data for error correction to every certain data bits to be stored in a memory cell array, the memory cell array including a plurality of memory cells arrayed therein, the memory cells being capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage;
- a frame converter circuit configured to uniformly divide frame data containing the data bits and the parity data into N pieces of subframe data;
- and
- a programming circuit configured to store the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits,
- wherein the parity data is stored in the N sub-pages in order beginning from a sub-page with the smallest variation in bits between adjacent threshold voltage states.
Dependencies are inferred from the claim text.