Technique for initializing data and instructions for core functional pattern generation in multi-core processor

A method of introducing processor core functional tests into a memory space addressable by at least one processor core of a system on a chip (SoC) integrated circuit, the method comprising:

• scanning data pattern target and data pattern selection information from off-chip into respective fields of control registers of an on-chip loader;
• scanning at least a first data pattern from off-chip into on-chip data pattern storage accessible by the on-chip loader;
• under control of the on-chip loader, writing data pattern information to a first set of plural data locations in the memory space addressable by the processor core, wherein the data patterns written and the written-to data locations of the first set are respectively selected based on the data pattern target and the data pattern selection information scanned from off-chip;
• scanning at least instruction target and instruction selection information from off-chip into respective fields of the control registers of the on-chip loader;
• and
• under control of the on-chip loader, writing instructions to a second set of plural instruction locations in the addressable memory space, wherein the instructions written and the written-to instruction locations of the second set are respectively selected based on the instruction target and instruction selection information scanned from off-chip,
• wherein at least one of the selected data patterns corresponds to the first data pattern and is sourced from the on-chip data pattern storage, and
• wherein the functional tests introduced into the memory space addressable by the processor core include both the data patterns and instructions executable by the processor core.

An apparatus comprising:

• at least one processor core, the at least one processor core suitable for executing instruction sequences from, and addressing data in, memory;
• an on-chip cache operatively coupled between the at least one processor core and an interface to the memory;
• and
• an on-chip functional test loader coupled to introduce, based on data pattern target and data pattern selection information scanned from off-chip into respective fields of control registers, at least a first portion of a core functional test into the on-chip cache, wherein the introduced first portion of the core functional test includes at least a first data pattern scanned from off-chip into on-chip data pattern storage accessible by the on-chip functional test loader, the on-chip functional test loader coupled to further introduce, based on instruction target and instruction selection information scanned from off-chip into respective fields of control registers, at least a second portion of the core functional test into the on-chip cache, wherein the introduced second portion of the core functional test includes at least one opcode for execution by the processor core.

A method of introducing processor core functional tests into a memory space addressable by least one processor core of a system on a chip (SoC) integrated circuit, the method comprising:

• scanning both data pattern targets and data pattern selections from off chip into first respective fields of control registers of an on-chip loader;
• scanning both instruction targets and opcode selections from off chip into second respective fields of the control registers of the on-chip loader;
• and
• under control of the on-chip loader, writing data patterns and opcodes to respective data and instruction locations in the addressable memory space,
• wherein the data patterns written and the written-to data locations are selected based on the data pattern targets and the data pattern selections scanned from off-chip, and wherein the opcodes written and the written-to instruction locations are selected based on the instruction targets and opcode selections scanned from off-chip.