Modulated clock, an IC including the modulated clock and a method of providing a modulated clock signal for power control

A method of providing a modulated clock signal for at least a portion of an integrated circuit, comprising:

• receiving a clock signal having a first frequency;
• generating a digital control stream;
• and
• providing a modulated clock signal in response to said clock signal and said digital control stream, wherein said modulated clock signal has an effective frequency that is different than said first frequency and said digital control stream is a pseudo-random data stream generated to reduce harmonic frequency emissions.

An integrated circuit, comprising:

• a clock configured to generate a base clock signal having a first frequency;
• a logic block of logic elements that are driven by a clock signal;
• and
• a modulated clock, including;
• a clock controller configured to generate a digital control stream;
• and
• clock logic circuitry configured to receive said digital control stream and said base clock signal and further configured to employ said digital control stream to reduce clock pulses of said base clock signal to provide a modulated clock signal for said logic block, wherein said modulated clock signal has an effective frequency that is less than said first frequency and said digital control stream is a pseudo-random data stream generated to reduce harmonic frequency emissions.

A library of standard logic elements for including in an integrated circuit, comprising:

• a standard logic element corresponding to a modulated clock, including:
• a clock controller configured to generate a digital control stream that is a pseudo-random data stream generated to reduce harmonic frequency emissions;
• and
• clock logic circuitry configured to receive said digital control stream and a base clock signal having a first frequency and further configured to employ said digital control stream to reduce clock pulses of said base clock signal to provide a modulated clock signal, said modulated clock signal having an effective frequency that is less than said first frequency.

An integrated circuit, comprising:

• a clock configured to generate a base clock signal having a first frequency;
• a logic block of logic elements that are driven by a clock signal;
• and
• a modulated clock, including;
• a clock controller configured to generate a digital control stream;
• and
• clock logic circuitry configured to receive said digital control stream, said base clock signal and an additional digital control stream that differs from said digital control stream, said clock logic circuitry further configured to employ said digital control stream to reduce clock pulses of said base clock signal to provide a modulated clock signal and employ said additional digital control stream to reduce clock pulses of said base clock signal to provide an additional modulated clock signal for said logic block, wherein said modulated clock signal and said additional modulated clock signal have an effective frequency that is different than said first frequency.