Software programmable timing architecture

A computer-implemented method to generate a control signal, comprising steps of:

• (a) producing, by a processor, a first output count in response to a clock signal by generating first and second different free running counter outputs and selecting one of the first counter output and the second counter output as the first output count based upon a first control signal, the first control signal is independent of the first and second counter outputs;
• (b) simultaneously comparing the first output count with each of first and second stored count values;
• and
• (c) generating a particular type of output event at a first node corresponding to the control signal if the first output count corresponds to either of first and second stored count values.

A circuit comprising:

• a digital pattern generator configured to generate a pattern of digital signals at M nodes;
• a general purpose output controller configured to generate general purpose digital signals at N nodes the controller comprising:
• a memory configured to store simultaneously at least first and second count values, and
• a first cycle count comparison circuit configured to compare the first output count with each of the first and second stored count values simultaneously and to generate a particular type of output event at a first node if the first output count corresponds to either of the first and second stored count values;
• at least one first memory element configured to store particular values for M outputs of the circuit corresponding to the M nodes of the digital pattern generator and for N outputs of the circuit corresponding to the N nodes of the general purpose output controller;
• and
• a selection circuit configured to select, independently for each of the M outputs of the circuit, whether the particular value stored in the at least one first memory element or the corresponding output signal of the digital pattern generator is provided on that output, and further configured to select, independently for each of the N outputs of the circuit, whether a standby value stored in the at least one first memory element or the corresponding output signal of the general purpose output controller is provided on that output.