Multiprocessor electronic circuit including a plurality of processors and electronic data processing system
AssigneeInternational Business Machines Corporation
InventorsThomas Koehler, Thomas Fuchs, Ulrich Mayer, Chung-Lung Kevin Shum, Scott Barnett Swaney
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Abstract
A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.
Claims8
A multiprocessor electronic circuit comprising:
- a plurality of processors;
- a single cryptographic processing unit comprising a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and further comprising two cryptographic engines, a cipher engine and a hash engine, wherein an assignment of one of the two cryptographic engines to one of the plurality of processors is performed independently from an assignment of the other of the two cryptographic engines;
- and
- control logic for connecting the cryptographic processing unit to the plurality of processors and for temporarily assigning one of the two cryptographic engines to one of the plurality of processors.
An electronic data processing system comprising a multiprocessor electronic circuit, the multiprocessor electronic circuit comprising:
- a plurality of processors;
- a single cryptographic processing unit comprising a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and further comprising two cryptographic engines, a cipher engine and a hash engine, wherein an assignment of one of the two cryptographic engines to one of the plurality of processors is performed independently from an assignment of the other of the two cryptographic engines the;
- and
- control logic for connecting the cryptographic processing unit to the plurality of processors and for temporarily assigning one of the two cryptographic engines to one of the plurality of processors.
Dependencies are inferred from the claim text.