US 8,135,942 B2Granted

System and method for double-issue instructions using a dependency matrix and a side issue queue

AssigneeInternational Business Machines Corporation

InventorsChristopher M. Abernathy, Mary D. Brown, Todd A. Venton, John B. Griswell, Jr.

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Abstract

A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method places the second portion into a side issue queue. The method issues the second portion when the side issue queue indicates that the second portion is eligible for issue.

Claims16

Dependent claims

A method, comprising:

receiving a complex instruction comprising a first portion and a second portion;
setting an issue queue slot for the complex instruction;
allocating an execution unit for the execution of the complex instruction;
identifying first portion dependencies in the first portion;
identifying second portion dependencies in the second portion;
setting a dependency matrix slot based on the issue queue slot, the second portion, and the second portion dependencies;
determining whether the first portion dependencies have been satisfied, and in the event the first portion dependencies have been satisfied, issuing the first portion from the issue queue slot;
issuing the second portion from a side queue;
setting a consumers table slot based on the issue queue slot, the second portion, and the second portion dependencies;
issuing the second portion from the issue queue slot;
determining in a first test whether the second portion dependencies have been satisfied;
in the event the second portion dependencies have not been satisfied, forwarding the second portion to a side queue;
determining in a second test whether the second portion dependencies have been satisfied;
and
in the event the second portion dependencies have not been satisfied, waiting until the second portion dependencies have been satisfied.

12 more elements

A computer program product for double issue complex instructions, the computer program product comprising:

a non-transitory computer useable storage medium having computer useable program code embodied therewith, the computer useable program code comprising:
computer usable program code configured to receive a complex instruction comprising a first portion and a second portion;
computer usable program code configured to set an issue queue slot for the complex instruction;
computer usable program code configured to allocate an execution unit for the execution of the complex instruction;
computer usable program code configured to identify first portion dependencies in the first portion;
computer usable program code configured to identify second portion dependencies in the second portion;
computer usable program code configured to set a dependency matrix slot based on the issue queue slot, the second portion, and the second portion dependencies;
computer usable program code configured to determine whether the first portion dependencies have been satisfied, and to issue the first portion from the issue queue slot;
and
computer usable program code configured to issue the second portion from a side queue wherein the size queue is different from the issue queue.

7 more elements

A processor, comprising a computer program product for double issue complex instructions, the computer program product comprising:

a non-transitory computer useable storage medium having computer useable program code therewith, the computer useable program code comprising:
computer usable program code configured to receive a complex instruction comprising a first portion and a second portion;
computer usable program code configured to set an issue queue slot for the complex instruction;
computer usable program code configured to allocate an execution unit for the execution of the complex instruction;
computer usable program code configured to identify first portion dependencies in the first portion;
computer usable program code configured to identify second portion dependencies in the second portion;
computer usable program code configured to forward the second portion to a side queue;
computer usable program code configured to set a dependency matrix slot based on the issue queue slot, the second portion, and the second portion dependencies;
computer usable program code configured to determine whether the first portion dependencies have been satisfied, and to issue the first portion from the issue queue slot;
computer usable program code configured to determine whether the second portion dependencies have been satisfied;
computer usable program code configured to, in the event the second portion dependencies have not been satisfied, wait until the second portion dependencies have been satisfied;
computer usable program code configured to, in the event the second portion dependencies have been satisfied, mark the second portion as ready for issue;
computer usable program code configured to issue the second portion when it is the oldest ready instruction;
and
computer usable program code configured to de-allocate the side queue slot.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/199,971Filed 28 Aug 2008
Published: US 2010/0058033 A14 Mar 2010
Granted: 13 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/3842
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: speculative instruction execution
G06F 9/3885
Concurrent instruction execution, e.g. pipeline or look ahead: using a plurality of independent parallel functional units