Vector morphing mechanism for multiple processor cores
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
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Abstract
One embodiment of the invention provides a processor. The processor generally includes a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions and scheduling logic configured to issue a first issue group of instructions to the first processor core for execution and a second issue group of instructions to the second processor core for execution when the processor is in a first mode of operation and configured to issue one or more vector instructions for concurrent execution on the first and second processor cores when the processor is in a second mode of operation.
Claims20
A processor, comprising:
- a first and second processor core, each comprising:
- (i) a plurality of pipelined execution units configured to respectively execute a first and second issue group of multiple instructions and (ii) at least one of an instruction queue for delaying instruction execution and a target delay queue for holding results from instruction execution;
- and
- scheduling logic configured to, when the processor is in a base mode of operation, issue the first issue group to the first processor core for execution and the second issue group to the second processor core for execution and, when the processor is in a ganged mode of operation, issue one or more vector instructions to a morphed processor core formed from the first and second processor cores wherein each issue group comprises instructions issued in a single cycle;
- wherein each of the first and second processor cores is configured to, when the processor is in the base mode of operation, cascade execution of its respective issue group, using at least one of the instruction queue and the target delay queue;
- wherein the morphed processor core is configured to, when the processor is in the ganged mode of operation, cascade execution of the one or more vector instructions by increasing a queue depth of at least one of the instruction queue and the target delay queue of at least one of the first processor core and the second processor core.
A computing system, comprising:
- a first and second processor, each comprising:
- (i) a plurality of processor cores for executing one or more vector instructions and (ii) at least one of an instruction queue for delaying instruction execution and a target delay queue for holding results from instruction execution;
- and
- scheduling logic configured to, when the computing system is in a base mode of operation, issue one or more vector instructions to the first processor for execution and one or more vector instructions to the second processor for execution and, when the computing system is in a ganged mode of operation, issue an issue group of vector instructions for execution to a morphed processor formed from the first and second processor, wherein the issue group comprises instructions issued in a single cycle;
- wherein each of the first and second processors is configured to, when the computing system is in the base mode of operation, cascade execution of its respective one or more vector instructions, using at least one of the instruction queue and the target delay queue;
- wherein the morphed processor is configured to, when the computing system is in the ganged mode of operation, cascade execution of the issue group of vector instructions by increasing a queue depth of at least one of the instruction queue and the target delay queue of at least one of the first processor and the second processor.
Dependencies are inferred from the claim text.