ECC implementation in non-ECC components
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael John Haertel, R. Stephen Polzin, Andrej Kocev, Maurice Bennet Steinman
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Abstract
A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.
Claims14
A method comprising:
- receiving a logical address, wherein the logical address maps to a first physical address of a memory and a second physical address of the memory, wherein the first physical address is configured to store data and the second physical address configured to store an error correction code (ECC) corresponding to the data stored at the first physical address;
- translating the logical address into the first and second physical addresses, wherein translating the logical address into first and second physical addresses comprises permuting bits of the logical address such that the ECC's are stored in physical memory locations adjacent to physical locations in the memory in which data protected by the ECC's is stored, wherein said permuting is performed based on a page boundary, wherein the ECC's are stored adjacent to the page boundary such that a single row address and two column addresses are provided to access a block of data and its corresponding ECC;
- accessing the data from the first physical address over a data path;
- separately accessing the ECC over the data path;
- and
- checking integrity of the data using the ECC.
A memory subsystem comprising:
- a memory;
- a data path;
- and
- a memory controller coupled to the memory by the data path, wherein the memory controller is coupled to receive a logical address, and wherein the memory controller is configured to:
- translate the logical address into a first physical address of a memory and a second physical address of the memory, wherein the first physical address is configured to store data and the second physical address configured to store an error correction code (ECC) corresponding to the data stored at the first physical address, wherein the memory controller is configured to translate the logical address into first and second physical addresses by permuting bits of the logical address such that the ECC's are stored in physical memory locations adjacent to physical locations in the memory in which data protected by the ECC's is stored, wherein said permuting is performed based on a page boundary, and wherein the ECC's are stored adjacent to the page boundary such that a given block of data and its corresponding ECC are accessible by providing a single row address and two column addresses;
- access data from the first physical address in the memory via the data path;
- separately access the ECC from the second physical address via the data path;
- and
- check the integrity of the data using the ECC.
A method comprising:
- reserving a first portion of a memory for storing data;
- and
- reserving a second portion of the same memory for storing error correction codes (ECC's) protecting the data;
- wherein a logical address maps to a first physical address in the first portion of the memory and a second physical address in the second portion of the memory;
- and
- wherein the first physical address is located in a memory page, and wherein the second physical address is located in the same memory page, wherein the first and second physical addresses are obtained by permuting bits of the logical address such that the second physical address is adjacent to a page boundary, and wherein a given block of data and its corresponding ECC are accessible by providing a single row address and two column addresses.
Dependencies are inferred from the claim text.