Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator
AssigneeInternational Business Machines Corporation
InventorsRobert Tod Dimpsey, Frank Eliot Levine, Robert John Urquhart
Life of this patent
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Abstract
A method, apparatus, and computer instructions for providing hardware assistance to prefetch data during execution of code by a process or in the data processing system. In response to loading an instruction in the code into a cache, a determination is made by a processor unit as to whether a prefetch indicator is associated with the instruction. In response to the prefetch indicator being associated with the instruction, a pointer to a data structure identified by the prefetch indicator is selectively prefetched into the cache in the processor.
Claims19
A method in a data processing system for providing hardware assistance to prefetch data during execution of code by a processor in the data processing system, the method comprising:
- responsive to loading an instruction in the code into a cache, determining, by a processor unit, whether a prefetch indicator is associated with the instruction;
- and
- responsive to the prefetch indicator being associated with the instruction, selectively prefetching a pointer to a data structure identified by the prefetch indicator into the cache in the processor, wherein the selectively prefetching step includes:
- determining whether outstanding cache misses are present;
- and
- prefetching the data in response to a determination that a number of outstanding cache misses is less than a threshold.
A data processing system for providing hardware assistance to prefetch data during execution of code by a processor in the data processing system, the data processing system comprising:
- determining means, responsive to loading an instruction in the code into a cache, for determining, by the a processor unit, whether a prefetch indicator is associated with the instruction;
- and
- selectively prefetching means, responsive to the prefetch indicator being associated with the instruction, for selectively prefetching a pointer to a data structure identified by the prefetch indicator into the cache in the processor, wherein the selectively prefetching means includes:
- means for determining whether outstanding cache misses are present;
- and
- means for prefetching the data in response to a determination that a number of outstanding cache misses is less than a threshold.
A computer program product in a recordable-type computer readable medium for providing hardware assistance to prefetch data during execution of code by a processor in the data processing system, the computer program product comprising:
- first instructions, responsive to loading an instruction in the code into a cache, for determining, by the a processor unit, whether a prefetch indicator is associated with the instruction;
- and
- second instructions, responsive to the prefetch indicator being associated with the instruction, for selectively prefetching a pointer to a data structure identified by the prefetch indicator into the cache in the processor, wherein the second instructions includes:
- first sub-instructions for determining whether outstanding cache misses are present;
- and
- second sub-instructions for prefetching the data in response to a determination that a number of outstanding cache misses is less than a threshold.
A method in a data processing system for providing hardware assistance to prefetch data during execution of code by a processor in the data processing system, the method comprising:
- responsive to loading an instruction in the code into a cache, determining, by a processor unit, whether a prefetch indicator is associated with the instruction, wherein the processor unit is selected from one of an instruction cache, a data cache, and a load/store unit;
- and
- responsive to the prefetch indicator being associated with the instruction, selectively prefetching a pointer to a data structure identified by the prefetch indicator into the cache in the processor, wherein the selectively prefetching step includes:
- determining that outstanding cache misses are present;
- and
- prefetching the data in response to a determination that a number of the outstanding cache misses is less than a threshold, and wherein selectively prefetching step further includes:
- determining to replace cache lines;
- and
- prefetching the data in response to a determination that a number of the cache lines chosen to be replaced is greater than a threshold.
Dependencies are inferred from the claim text.