Methods and systems for reducing interrupt latency by using a dedicated bit
AssigneeAltera Corporation
InventorJames L. Ball
Life of this patent
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Abstract
A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to generate a second interrupt, and a processor. The processor includes a shadow set that stores data used to service the first interrupt. The processor receives the second interrupt and receives a designation of the shadow set to service the second interrupt. The processor determines, based on a dedicated bit, whether the shadow set is used to service the first interrupt upon receiving the second interrupt.
Claims23
A system for reducing interrupt latency, said system comprising:
- a first interrupt source configured to generate a first interrupt;
- a second interrupt source configured to generate a second interrupt;
- and
- a processor including a plurality of shadow sets configured to store data used to service interrupts, wherein said processor receives the first interrupt and a designation of a first shadow set to service said first interrupt,
- wherein said processor receives the second interrupt and receives a designation of a shadow set to service the second interrupt,
- wherein said processor is further configured to determine, based on a dedicated bit, whether said shadow set to service the second interrupt is said first shadow set.
A processor for reducing interrupt latency, said processor comprising:
- a plurality of shadow sets configured to store data used to service interrupts, wherein said processor receives a first interrupt received from a first interrupt source and a designation of a first shadow set to service said first interrupt,
- wherein said processor receives a second interrupt received from a second interrupt source and receive a designation of a shadow set to service the second interrupt,
- wherein said processor is further configured to determine, based on a dedicated bit, whether said shadow set to service the second interrupt is said first shadow set.
A method for reducing interrupt latency, said method comprising:
- receiving a first interrupt from a first interrupt source;
- receiving a second interrupt from a second interrupt source;
- servicing the first interrupt;
- storing data used to service the first interrupt within a first shadow set;
- receiving a designation of a shadow set to service the second interrupt;
- and
- determining, based on a dedicated bit, whether the shadow set to service the second interrupt is said first shadow set.
Dependencies are inferred from the claim text.