Dynamically configurable serial data communication interface
AssigneeSkyworks Solutions, Inc.
InventorThomas Obkircher
Life of this patent
Estimating the term…
Abstract
A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.
Claims32
A method for controlling a serial peripheral interface, comprising:
- monitoring serial peripheral interface signal lines including a data signal line, a clock signal line, and a select signal line;
- detecting a plurality of clock signal transitions on the clock signal line;
- detecting a plurality of data signal transitions on the data signal line in synchronism with clock signal transitions;
- detecting initiation of one of a data read and data write operation in accordance with a first protocol in response to a first combination of one or more signals on one or more of the data signal line, the clock signal line, and the select signal line;
- and
- detecting initiation of one of a data read and data write operation in accordance with a second protocol in response to a second combination of one or more signals on one or more of the data signal line, the clock signal line, and the select signal line;
- performing a data read operation upon a register identified by address bits received serially on the data signal line following detection of the initiation of a data read operation;
- and
- performing a data write operation upon a register identified by address bits received serially on the data signal line following detection of the initiation of a data write operation.
A serial peripheral interface controller connectable to a data signal line, a clock signal line, and a select signal line, comprising:
- a register bank, the register bank having a plurality of data storage registers;
- and
- control logic programmed or configured to:
- detect a plurality of bit transitions on the data signal line in synchronism with clock signal transitions;
- detect initiation of one of a data read and data write operation in accordance with a first protocol in response to a first combination of one or more signals on one or more of the data signal line, the clock signal line, and the select signal line;
- and
- detect initiation of one of a data read and data write operation in accordance with a second protocol in response to a second combination of one or more signals on one or more of the data signal line, the clock signal line, and the select signal line;
- perform a data read operation upon a register of the register bank identified by address bits received serially on the data signal line following detection of the beginning of a data read operation;
- and
- perform a data write operation upon a register of the register bank identified by address bits received serially on the data signal line following detection of the beginning of a data write operation.
Dependencies are inferred from the claim text.