Back to results
US 8,135,878 B1Granted
Method and apparatus for improving throughput on a common bus
AssigneeTellabs San Jose, Inc.
InventorNaveen K. Jain
Life of this patent
Estimating the term…
Abstract
A bus scheduling device having a group of direct memory access (“DMA”) engines, a group of target modules (“TM”), a read pending memory, and a bus arbiter is disclosed. A common bus, which is coupled with the DMA engines, TMs, and the read pending memory, is employed in the device for data transmission. DMA engines are capable of transmitting and receiving data to and from TMs via the common bus. The read pending memory is capable of storing information indicating the read status of the DMA engines. The arbiter or bus arbiter arbitrates bus access in response to a bus allocation scheme and the information stored in the read pending memory.
Claims21
A method for bus accessing, comprising:
- receiving a first bus request for first data from a first direct memory access (“DMA”) engine to a first target module (“TM”);
- allocating a single data bus to the first DMA engine;
- setting a first busy signal from the first TM to an active state base on time required to retrieve the first data is greater than one of a plurality of equally partitioned time slots;
- detecting the first busy signal from the first TM requesting additional time for retrieving the first data;
- setting a first read pending indicator in a read pending memory in response to the first busy signal;
- releasing the single data bus in response to the first busy signal and setting of the first read pending indicator;
- continuing retrieving the first data from a memory device to the first TM while the single data bus is allocated to another DMA engine after the single data bus was released;
- and
- reallocating the single data bus back to the first DMA engine for transferring the first data from the first TM to the first DMA engine when the first busy signal is deactivated.
6 more elements
A bus scheduling device, comprising:
- a single bus configured to transmit data;
- a plurality of direct memory access (“DMA”) engines coupled to the single bus and transmitting a data packet to a system controller, wherein a first DMA engine transmits a first bus request for a first data to a first target module (“TM”);
- a plurality of TMs coupled to the single bus wherein one of the plurality of TMs transmits the data packet to one of the plurality of DMA engines, wherein the data packet includes the first data, and the first TM provides a first busy signal to request additional time for retrieving the first data from a memory device to the first TM, as time required to retrieve the first data is greater than one of a plurality of equally partitioned time slots;
- a read pending memory coupled to the bus and storing information indicating read status for the plurality of DMA engines, wherein a first read pending indicator is set in response to the first busy signal;
- and
- a bus arbiter coupled to the single bus and scheduling bus access in response to a bus allocation scheme and the information stored in the read pending memory, wherein the single bus is allocated to the first DMA engine for the first data and is released in response to detecting the first busy signal and setting the first read pending indicator, the single bus is then allocated to another DMA engine after the release, and the single bus is then reallocated back to the first DMA engine for transferring the first data from the first TM to the first DMA engine when the first busy signal is deactivated.
3 more elements
An apparatus for bus accessing, comprising:
- means for receiving a first bus request for first data from a first direct memory access (“DMA”) engine to a first target module (“TM”);
- means for allocating a single data bus to the first DMA engine;
- means for setting a first busy signal from the first TM to an active state base on time required to retrieve the first data is greater than one of a plurality of equally partitioned time slots;
- means for detecting the first busy signal from the first TM requesting additional time for retrieving the first data;
- means for setting a first read pending indicator in a read pending memory in response to the first busy signal;
- means for releasing the single data bus in response to the first busy signal and setting of the first read pending indicator;
- means for continuing retrieving the first data from a memory device to the first TM while the single data bus is allocated to another DMA engine after the single data bus was released;
- and
- means for reallocating the single data bus back to the first DMA engine for transferring the first data from the first TM to the first DMA engine when the first busy signal is deactivated.
6 more elements
Dependencies are inferred from the claim text.