Streaming data engine
AssigneeMarvell International Ltd.
InventorsMoinul H. Khan, Mark N. Fullerton, Bradley C. Aldrich, Anitha Kona
Life of this patent
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Abstract
In one or more embodiments, a method, computer-readable media, system and or modules are capable of generating an address for a multimedia data block included in a stream of multimedia data. The address can be maintained in one or more local registers. The one or more local registers can be linked to one or more processor registers associated with a processor to synchronize communication of the stream of multimedia data with the processor.
Claims28
A streaming data engine comprising:
- a buffer communicably coupled with a memory interface and a reduced instruction set computer (RISC) processor, the buffer configured to store a multimedia data block included in a stream of multimedia data accessible via the memory interface;
- an address generator configured to generate an address for the multimedia data block stored in the buffer;
- a local register configured to maintain the address generated for the multimedia data block;
- and
- a linkage table configured to link the local register that maintains the address generated for the multimedia data block to a register associated with the RISC processor effective to enable the multimedia data block stored in the buffer to be accessed by the RISC processor without receiving an explicit processor instruction.
A method comprising:
- storing a multimedia data block included in a stream of multimedia data in a buffer, the multimedia data block accessible via a memory interface;
- generating an address for the multimedia data block stored in the buffer;
- and
- linking a local register that maintains the address to a processor register associated with a reduced instruction set computer (RISC) processor effective to enable the multimedia data block stored in the buffer to be accessed by the RISC processor without receiving an explicit processor instruction.
One or more computer-readable memory devices embodying processor-executable instructions that, when executed by a processor, implement an address generator of a streaming data engine to:
- store a multimedia data block included in a stream of multimedia data in a buffer, the multimedia data block accessible via a memory interface;
- generate an address for the multimedia data block stored in the buffer;
- and
- link a local register that maintains the address to a processor register included in a reduced instruction set computer (RISC) processor effective to enable the multimedia data block stored in the buffer to be accessed by the RISC processor without receiving an explicit processor instruction.
A System-on-Chip (SoC) comprising:
- a reduced instruction set computer (RISC) processor for processing data, the data accessible via a memory interface;
- a RISC co-processor having an engine and a register, and configured to process multimedia data blocks of a stream of multimedia data for the RISC processor;
- a streaming data engine comprising:
- a buffer communicatively coupled with the memory interface, the buffer configured to store one of the multimedia data blocks read from the memory interface;
- an address generator configured to generate an address for the multimedia data block stored in the buffer;
- a local register configured to maintain the address generated for the multimedia data block;
- and
- a linkage table configured to link the local register of the streaming data engine with the register of the RISC co-processor effective to enable the multimedia data block stored in the buffer to be accessed by the RISC co-processor without receiving an explicit processor instruction.
Dependencies are inferred from the claim text.