Standard cell for arithmetic logic unit and chip card controller
OwnerThomas Kuenemundinventor
Life of this patent
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Abstract
A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.
Claims17
A cell for an arithmetic logic unit comprising:
- a mirror adder circuit comprising:
- a first masked input a*;
- a second masked input b*;
- a masked carry bit input ci*;
- a first control input xe0 and a second control input xe1;
- and
- a circuit connected to the first masked input a*, the second masked input b*, the masked carry bit input ci*, the first control input xe0, and the second control input xe1, the circuit having a first output co*_n and a second output s*_n,
- wherein the mirror adder circuit comprises a plurality of transistors, wherein the masked carry bit input ci*, the first control input xe0 and the second control input xe1 are applied to different ones of the transistors of the mirror adder circuit;
- and
- a control unit connected to the circuit, the control unit having a first mask bit input kp, a second mask bit input kp−1, a first control bit input n0, and a second control bit input n1,
- wherein the control unit is configured to generate values for the masked carry bit input ci*, the first control input xe0 and the second control input xe1 as a function of values of the first mask bit input kp, the second mask bit input kp−1, the first control bit input n0 and the second control bit input n1,
- wherein, to implement a first operation, the control unit is configured to generate the values of the first control input xe0 and the second control input xe1 to correspond to the value of the masked carry bit input ci* so that the second output is an inverted masked sum bit s*_n of a masked arithmetic addition of the first masked input a*, the second masked input b* and the masked carry bit input ci*, and the first output co*_n is a masked inverted carry-out bit.
A circuitry for an ALU cell comprising:
- a first mask bit input kp−1;
- a second mask bit input
- a masked carry bit input ci′;
- two control bit inputs n0, n1;
- and
- a circuit outputting a remasked carry bit ci* as a function of the first mask bit input kp, the second mask bit input kp−1 the masked carry bit input ci′, and the two control bit inputs n0, n1, the circuit having two control outputs xe0, xe1,
- wherein, to implement a first operation, the circuit is configured to generate the values of the first control output xe0 and the second control output xe1 to correspond to the value of the remasked carry bit ci*.
A control circuitry for an ALU cell comprising:
- a current mask bit input kp;
- a previous mask bit input kp−1 inputting the mask bit from an immediately upstream ALU cell;
- a masked carry bit input ci′;
- and
- a circuit outputting a remasked carry bit ci* as a function of the current mask bit input kp, the previous mask bit input kp−1 and the masked carry bit input ci′, the circuit having two control outputs xe0, xe1 as a function of the current mask bit input kp and the previous mask bit input kp−1,
- wherein, to implement a first operation, the circuit is configured to generate the values of the first control output xe0 and the second control output xe1 to correspond to the value of the remasked carry bit ci*.
A processing unit comprising:
- a control unit adapted to generate a remasked carry input ci*, a first control input xe0, and a second control input xe1 as a function of a first control bit input n0 and a second control bit input n1, wherein the control unit is configured to generate the first control input xe0 and the second control input xe1 to correspond to the remasked carry input ci*;
- and
- a data unit adapted to generate a masked inverted carry output co*_n and a masked inverted sum bit s*_n based on the remasked carry input ci*, the first control input xe0, and the second control input xe1.
Dependencies are inferred from the claim text.