US 8,135,557 B2 · Apparatus for testing semiconductor integrated circuit and method for testing semiconductor integrated circuit

Abstract

An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector. The simulator includes an asynchronous transfer point extraction unit that extracts an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain that are input through the input part, a simulation unit that calculates a logic circuit output of the semiconductor integrated circuit by performing a simulation in accordance with the circuit description data and the first test vector that are input through the input part, and a second test vector generation unit that generates a second test vector by changing a signal of an asynchronous transfer point of the logic circuit output calculated by the simulation unit in accordance with the asynchronous transfer point extracted by the asynchronous transfer point extraction unit.

Claims14

Dependent claims

A testing apparatus, comprising:

an input part configured to input circuit description data in which a circuit structure of a semiconductor integrated circuit is described, a clock domain of the semiconductor integrated circuit, and a first test vector used to test a normal operation of the semiconductor integrated circuit;
and
an asynchronous transfer point extraction unit configured to extract an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain;
a simulation unit configured to calculate a logic circuit output and a first external output in the normal operation of the semiconductor integrated circuit in accordance with the circuit description data and the first test vector;
and
a second test vector generation unit configured to randomly select any simulation time and generate a second test vector used to test a violation of the semiconductor integrated circuit by inverting a signal of an asynchronous transfer point of the logic circuit output when the signal of the asynchronous transfer point of the logic circuit output is not identified in the selected simulation time, wherein
the simulation unit calculates a second external output in the violation of the semiconductor integrated circuit in accordance with the circuit description data and the second test vector.

4 more elements

A method for causing a testing apparatus to test a semiconductor integrated circuit, comprising:

inputting circuit description data in which a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector used to test a normal operation of the semiconductor integrated circuit;
extracting an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and clock domain;
calculating a logic circuit output and a first external output in the normal operation of the semiconductor integrated circuit in accordance with the input circuit description data and the first test vector;
randomly selecting any simulation time and generating a second test vector used to test a violation of the semiconductor integrated circuit by inverting a signal of an asynchronous transfer point of the logic circuit output when the signal of the asynchronous transfer point of the logic circuit output is not identified in the selected simulation time;
and
calculating a second external output in the violation of the semiconductor integrated circuit in accordance with the circuit description data and the second test vector, wherein the method for causing the testing apparatus to test the semiconductor integrated circuit is stored in a memory and is executed by a simulator.

3 more elements

Dependencies are inferred from the claim text.

Apparatus for testing semiconductor integrated circuit and method for testing semiconductor integrated circuit

Life of this patent

Apparatus for testing semiconductor integrated circuit and method for testing semiconductor integrated circuit

Life of this patent

Abstract

Claims14