Adaptive clock and equalization control systems and methods for data receivers in communications systems
AssigneeInternational Business Machines Corporation
InventorsTroy James Beukema, William Richard Kelly
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Abstract
Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer.
Claims20
A method for dynamically adapting a line equalization control system in a data receiver, comprising act of:
- receiving an input signal comprising a serial data stream;
- applying the input signal to a plurality of sampling paths, including an amplitude sampling path and data sampling path;
- sampling the input signal in the amplitude sampling path using an amplitude sampling clock signal CLK_A to generate an amplitude sampled signal;
- sampling the input signal in the data sampling path using a data sampling clock signal CLK_D to generate a data sampled signal;
- performing an adaptive DFE (decision-feedback equalization) process using the amplitude and data sampled signals;
- performing an adaptive clock alignment process during run-time operation of the receiver to dynamically and independently adjust phases of the data and amplitude sampling clock signals to maintain alignment of the data and amplitude clock signals based, in part, on feedback from the DFE process.
A data receiver comprising:
- an input port for receiving an input signal comprising a serial data stream;
- an adaptive sampling clock system to generate a plurality of sampling clock signals, including a amplitude and data sampling clock signals, to sample the input signal applied to each of a plurality of sampling paths, including an amplitude sampling path and data sampling path to generate a data sampled signal and an amplitude sampled signal;
- and
- an adaptive DFE (decision-feedback equalization) control system that performs a line equalization process using the amplitude and data sampled signals;
- wherein the adaptive sampling clock system is adapted to perform an adaptive clock alignment process during run-time operation of the receiver to dynamically and independently adjust phases of the data and amplitude sampling clock signals to maintain alignment of the data and amplitude clock signals based, in part, on feedback from the adaptive DFE control system.
Dependencies are inferred from the claim text.