Reconfigurable chip level equalizer architecture
AssigneeTexas Instruments Incorporated
InventorsAntonio F. Mondragon-Torres, Steven P. Pekarich, Timothy M. Schmidl, Gibong Jeong, Aris Papasakellariou, Anand G. Dabak, Eko N. Onggosanusi
Life of this patent
Estimating the term…
Abstract
A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.
Claims16
An apparatus, comprising:
- two or more adaptive equalizers;
- a plurality of operation blocks that interconnect the adaptive equalizers;
- a first control mechanism that configures the adaptive equalizers and the plurality of operational blocks according to different signal delay profiles;
- a second control mechanism that disables at least one of said plurality of operational blocks according to the different signal delay profiles;
- and
- a third control mechanism that disables a computation resource of at least one of said adaptive equalizers according to the different delay profiles.
An apparatus, comprising:
- two or more adaptive equalizers;
- a plurality of operation blocks that interconnect the adaptive equalizers;
- a first control mechanism that configures the adaptive equalizers and the plurality of operational blocks according to different signal delay profiles;
- a second control mechanism that disables at least one of said plurality of operational blocks according to the different signal delay profiles;
- and
- a third control mechanism that disables a computation resource of at least one of said adaptive equalizers according to the different delay profiles, the first, second, and third control mechanisms comprise multiplexers that receive control signal according to the different delay profiles.
A method, comprising:
- receiving a multi-path signal profile;
- determining attributes of the multi-path signal profile, comprising determining an amount of energy in a single sub-signal of the multi-path profile if the length of the multi-path signal profile is less than a maximum number of taps of a single adaptive equalizer;
- and
- operating two or more adaptive equalizers, computational resources of the two or more adaptive equalizers, and operational blocks interconnecting said two or more adaptive equalizers according to said attributes of the multi-path signal profile.
A system comprising:
- two or more adaptive equalizers;
- a plurality of operational blocks;
- a means for selectively interconnecting the two or more adaptive equalizers and the plurality of operational blocks according to the attributes of a signal profile;
- and
- a means for disabling a computation resource of at least one of the two or more adaptive equalizers according to said attributes of the signal profile, the means for selectively interconnecting and the means for disabling comprising a plurality of multiplexers.
Dependencies are inferred from the claim text.