High-speed compression architecture for memory
AssigneeBAE Systems Information and Electronic Systems Integration Inc.
InventorJeffrey T. Feng
Life of this patent
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Abstract
Memory design techniques are disclosed that provide a high compression ratio at no loss in speed. The techniques can be embodied, for instance, in heterojunction bipolar transistor (HBT) based ROMs. By embedding compression logic (e.g., XOR) functionality directly into the address decoders and sense amplifiers of the memory device, a high compression ratio is achieved at no loss in speed. For example, the logic-based compression functionality can be directly implemented into the buffers that form the address decoder as well as the sense amplifiers.
Claims20
A memory device comprising:
- a memory cell array including rows and columns of bit cells for storing bit data;
- an address decoder having a plurality of buffers each operatively coupled to a corresponding row decoder configured for selecting a corresponding row of the memory cell array, each address decoder buffer configured with an integrated address reversal function;
- and
- a sense amplifier having a plurality of buffers each operatively coupled to a corresponding column of the memory cell array, each sense amplifier buffer configured with an integrated sign-inversion function;
- wherein the integrated address reversal and sign-inversion functions enable an X:1 compression ratio for the memory device with no increase in access time, where X is greater than 1.
A memory device comprising:
- a memory cell array including rows and columns of bit cells for storing bit data;
- an address decoder having a plurality of buffers each operatively coupled to a corresponding row decoder configured for selecting a corresponding row of the memory cell array, each address decoder buffer configured with an integrated address reversal function that is implemented with an XOR logic function;
- and
- a sense amplifier having a plurality of buffers each operatively coupled to a corresponding column of the memory cell array, each sense amplifier buffer configured with an integrated sign-inversion function that is implemented with an XOR logic function;
- wherein the integrated address reversal and sign-inversion functions enable a 4:1 compression ratio for the memory device with no increase in access time.
A system, comprising:
- a direct digital synthesizer (DDS) operatively coupled with a memory device, the memory device comprising:
- cell array including rows and columns of bit cells for storing bit data;
- an address decoder having a plurality of buffers each operatively coupled to a corresponding row decoder configured for selecting a corresponding row of the memory cell array, each address decoder buffer configured with an integrated address reversal function;
- and
- a sense amplifier having a plurality of buffers each operatively coupled to a corresponding column of the memory cell array, each sense amplifier buffer configured with an integrated sign-inversion function;
- wherein the integrated address reversal and sign-inversion functions enable an X:1 compression ratio for the memory device with no increase in access time, where X is greater than 1.
Dependencies are inferred from the claim text.