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US 8,134,883 B2Granted
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsMunehiro Kozuma, Yoshiyuki Kurokawa
Life of this patent
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Abstract
A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.
Claims9
A semiconductor device comprising:
- a memory circuit;
- and
- a central processing unit configured to execute a program based on data stored in the memory circuit,
- wherein the memory circuit comprises:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, and wherein the memory cells comprise first memory cells in which a semiconductor element is provided and second memory cells in which a semiconductor element is not provided,
- wherein the word lines comprise a first word line not connected to the first memory cells, and
- wherein the memory circuit is configured to store data of NOP command of the central processing unit at a row corresponding to the first word line.
7 more elements
A semiconductor device comprising:
- a memory circuit;
- and
- a dedicated circuit configured to execute an arithmetic operation based on data stored in the memory circuit,
- wherein the memory circuit comprises:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, and
- wherein the memory cells comprise first memory cells and second memory cells,
- wherein the word lines comprise a first word line not connected to the first memory cells,
- wherein each of the first memory cells comprises a first base insulating layer, a semiconductor layer on the first base insulating layer, a first insulating film on the semiconductor layer, a conductive film on the first insulating film, a first inter layer insulating film on the conductive film, and
- wherein each of the second memory cells comprises a second base insulating layer, a second insulating film on the second base insulating layer, a second inter layer insulating film on the second insulating film.
9 more elements
A semiconductor device comprising:
- a memory circuit;
- a central processing unit configured to execute a program based on data stored in the memory circuit;
- and
- a dedicated circuit configured to execute an arithmetic operation based on data stored in the memory circuit,
- wherein the memory circuit comprises:
- word lines;
- bit lines intersecting the word lines;
- and
- memory cells provided at intersecting areas of the word lines and the bit lines, and
- wherein the memory cells comprise first memory cells in which a semiconductor element is provided and second memory cells in which a semiconductor element is not provided,
- wherein the word lines comprise a first word line not connected to the first memory cells, and
- wherein the memory circuit is configured to store data of NOP command of the central processing unit at a row corresponding to the first word line.
9 more elements
Dependencies are inferred from the claim text.