Semiconductor memory device having redundancy circuit for repairing defective unit cell, and method for repairing defective unit cell
AssigneeHynix Semiconductor Inc.
InventorKwi-Dong Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input.
Claims19
A semiconductor memory device comprising a plurality of banks, each of which includes a plurality of unit cells, wherein two or more adjacent banks of the plurality of banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input,
- wherein the redundancy circuit includes:
- a bank selection unit configured to output data of a bank including the defective unit cell between the two adjacent banks:
- a fuse unit configured to output location data locating the defective unit cell according to a row address for accessing the two adjacent banks;
- and
- a comparison unit configured to determine whether to perform a defect repair operation according to an output of the bank selection unit after comparing the location data output by the fuse unit with an input column address.
A semiconductor memory device comprising a redundancy circuit configured to perform a defect repair operation through stored data of a defective unit cell in two adjacent banks when an input address for accessing data corresponds to the defective unit cell,
- wherein the semiconductor memory device has a stack bank structure where column control regions of the two banks are in contact with each other,
- wherein the redundancy circuit is disposed between the two adjacent banks and includes:
- a bank selection unit configured to output data of one of the two adjacent banks including the defective unit cell;
- a fuse unit configured to output location data locating the defective unit cell according to a row address for accessing the two adjacent banks;
- and
- a comparison unit configured to determine whether to perform the defect repair operation according to an output of the bank selection unit after comparing the location data output by the fuse unit with an input column address.
A method of repairing a defective unit cell in a semiconductor memory device, the method comprising:
- storing location data locating a unit cell of two adjacent banks;
- outputting column location data locating the defective unit cell, the defective unit cell having a row address in the two banks;
- comparing the column location data with a column address;
- and
- notifying whether to perform a defect repair operation according to which bank the defective unit cell belongs to between the two banks, when the column location data is consistent with the column address.
A semiconductor memory device, comprising:
- a fuse unit configured to store row and column address data of a defective unit cell of two adjacent banks, and to output the column address data of the defective unit cell according to row access data;
- a bank selection unit configured to transfer the row access data and column access data of the two banks, and to output location data locating one of the two banks including the defective unit cell;
- and
- a comparison unit configured to compare the column access data output from the bank selection unit with the column address data output from the fuse unit, and to determine whether to perform a defect repair operation according to the location data of a bank including the defective unit cell, which is output from the bank selection unit, when the column access data from the bank selection unit is consistent with the column address data from the fuse unit.
Dependencies are inferred from the claim text.