Semiconductor device having delay control circuit
AssigneeElpida Memory, Inc.
InventorKyoichi Nagata
Life of this patent
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Abstract
A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.
Claims11
A semiconductor device, comprising:
- a delay control circuit that generates an operation timing signal by delaying a reference signal by a predetermined delay amount;
- a first delay circuit having a plurality of first delay elements connected in series;
- a second delay circuit having a plurality of second delay elements connected in series, the first and second delay elements operating different conditions, respectively;
- a detection circuit that detects a difference in propagation speed of a pulse signal simultaneously input to the first and second delay circuits;
- and
- a setting circuit that sets the delay amount of the delay control circuit based on a detection result from the detection circuit,
- wherein the first delay elements and the second delay elements differ from each other in a fan-out.
A semiconductor device, comprising:
- a delay control circuit that generates an operation timing signal by delaying a reference signal by a predetermined delay amount;
- a first delay circuit having a plurality of first delay elements connected in series;
- a second delay circuit having a plurality of second delay elements connected in series, the first and second delay elements operating different conditions, respectively;
- a detection circuit that detects a difference in propagation speed of a pulse signal simultaneously input to the first and second delay circuits;
- a setting circuit that sets the delay amount of the delay control circuit based on a detection result from the detection circuit;
- a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each arranged at an associated one of intersections of the word lines and the bit lines;
- a word driver that selects any one of the word lines;
- and
- a plurality of sense amplifiers each connected to corresponding one of the bit lines, wherein
- the reference signal is a signal synchronized with an activation timing of the word driver, and
- the operation timing signal is a signal for activating the sense amplifiers.
A semiconductor device, comprising:
- a delay control circuit that generates an operation timing signal by delaying a reference signal by a predetermined delay amount;
- a first delay circuit having a plurality of first delay elements connected in series;
- a second delay circuit having a plurality of second delay elements connected in series, the first and second delay elements operating different conditions, respectively;
- a detection circuit that detects a difference in propagation speed of a pulse signal simultaneously input to the first and second delay circuits;
- a setting circuit that sets the delay amount of the delay control circuit based on a detection result from the detection circuit;
- a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each arranged at an associated one of intersections of the word lines and the bit lines;
- a word driver that selects any one of the word lines;
- a plurality of sense amplifiers each connected to corresponding one of the bit lines;
- and
- a column switch that selects any one of the sense amplifiers, wherein
- the reference signal is a signal synchronized with an activation timing of the word driver, and
- the operation timing signal is a signal for activating the column switch.
Dependencies are inferred from the claim text.