Dynamic leakage control for memory arrays

A method comprising:

• comparing a voltage level present on a virtual voltage rail to a reference voltage, wherein the virtual voltage rail is coupled to a memory sub-array;
• providing an output signal depending on a result of said comparing;
• and
• activating a switching circuit depending upon the output signal, wherein the switching circuit, when activated, pulls the voltage level present on the virtual voltage rail toward a voltage level present on a corresponding voltage supply node
• comprising periodically enabling a comparator to perform said comparing;
• and
• controlling a frequency at which the comparator is periodically enabled to perform said comparing based on a value provided by a programmable unit configured to store one or more values to control the frequency.

A memory circuit comprising:

• a plurality of memory cells coupled to receive power through a first node;
• a switching circuit coupled between the first node and a voltage supply node;
• a comparator coupled to compare a voltage level at the first node to a reference voltage level and configured to generate an output signal depending on the comparison;
• wherein the switching circuit is configured to electrically coupled the first node to the voltage supply node when in a first state and is configured to electrically isolate the first node from the voltage supply node when in a second state, wherein the first and second states of the switching circuit are dependent upon the output signal;
• wherein the memory circuit further comprises a timing unit coupled to provide an enable signal to the comparator, and wherein the comparator is configured to be enabled during a first phase of the clock signal and configured to be disabled during a second phase of the clock signal.

A memory circuit comprising:

• a static random access memory (SRAM) sub-array coupled to a virtual voltage rail;
• and
• a leakage control circuit including:
• a switching circuit having a first terminal coupled to the virtual voltage rail and a second terminal coupled to a corresponding voltage rail;
• and
• a comparator having a first input terminal coupled to the virtual voltage rail and a second input terminal coupled to receive a reference voltage, wherein the comparator is configured to compare a voltage level present on the virtual voltage rail to the reference voltage and to provide an output signal based on the comparison;
• wherein the switching circuit is configured to cause the voltage level present on the virtual voltage rail to be pulled toward a voltage level present on the corresponding voltage rail in response to the output signal;
• and
• wherein the leakage control circuit further includes a timer configured to generate a clock signal and coupled to provide the clock signal to an enable input of the comparator, wherein the comparator is configured to be enabled during a first phase of the clock signal and configured to be disabled during a second phase of the clock signal.

An integrated circuit comprising:

• a memory array including a plurality of sub-arrays, wherein each sub-array is coupled to receive power through a corresponding virtual voltage rail;
• and
• a plurality of leakage control circuits, wherein each sub-array is associated with a respective leakage control circuit coupled to its corresponding virtual voltage rail, wherein each respective leakage control circuit includes:
• a switching circuit coupled between the corresponding virtual voltage rail of the associated sub-array and a voltage supply node;
• a comparator coupled to compare a voltage level present on the corresponding virtual voltage rail to a reference voltage and configured to provide an output signal based on the comparison;
• a timing unit coupled to provide a signal to selectively enable the comparator;
• and
• a programmable unit configured to store one or more values to control a frequency and/or a duty cycle of the signal provided from the timing unit;
• wherein the switching circuit is configured to electrically couple the corresponding virtual voltage rail to the voltage supply node depending upon the output signal.