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AssigneeSamsung Electronics Co., Ltd.
InventorsDong-uk Choi, Jung-dal Choi, Choong-ho Lee, Sung-hoi Hur, Min-tai Yu
Estimating the term…
A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.
A flash memory device, comprising:
A method of erasing a flash memory device having first through nth memory cell transistors arranged in a row on a bulk region and connected to respective first through nth word lines, a first dummy cell transistor connected to the first memory cell transistor and having a first dummy word line, and a first selection transistor connected to the first dummy cell transistor and having a first selection line connected to the first selection transistor, the method comprising:
A method of programming a flash memory device having first through nth memory cell transistors arranged in a row on a bulk region and connected to respective first through nth word lines, a first dummy cell transistor connected to the first memory cell transistor and having a first dummy word line, and a first selection transistor connected to the first dummy cell transistor and having a first selection line connected to first selection transistor, the method comprising:
Dependencies are inferred from the claim text.