High-density non-volatile read-only memory arrays and related methods

A method of programming a read-only memory (ROM) array, the ROM array including a plurality of bit-lines, a plurality of word lines, and a plurality of transistors, each transistor including a gate terminal, a drain terminal, and a source terminal, the method comprising:

• coupling a first gate terminal of a first memory cell to a first word line of the plurality of word lines;
• determining a data value to be represented by the first memory cell;
• coupling a first drain terminal of the first memory cell to a first bit-line of the
• plurality of bit-lines and a first source terminal of the first memory cell to a second bit-line of the plurality of bit-lines when the determined data value comprises a zero value;
• coupling drain and source terminals of the first memory cell to each other when the determined data value and the next determined data value represent one values;
• and
• coupling one of the drain terminal and the source terminal of the first memory cell to one of the first and second bit-lines when the determined data value is one and the next data value is zero.

A memory array comprising:

• a plurality of word lines including first, second, third, fourth, and fifth word lines;
• a plurality of bit-lines including first and second bit-lines;
• a plurality of memory cells configured to represent data values, the plurality of memory cells comprising:
• a first transistor device including a first gate terminal coupled to the first word line, a first drain terminal, and a first source terminal coupled to the first drain terminal to represent a first one value;
• a second transistor device including a second gate terminal coupled to the second word line and including second drain and source terminals coupled to the first drain terminal to represent a second one value;
• a third transistor device including a third gate terminal coupled to the third word line and including a third drain terminal coupled to the first drain terminal, and a third source terminal coupled to a second bit-line of the plurality of bit-lines to represent a third one value;
• a fourth transistor device including a fourth gate terminal coupled to the fourth word line, a fourth drain terminal coupled to the third drain terminal, and a fourth source terminal coupled to a first bit-line of the plurality of bit-lines to represent a zero value;
• and
• a fifth transistor device including a fifth gate terminal coupled to the fifth word line and including fifth drain and source terminals coupled to the fourth source terminal to represent a fourth one value.