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US 8,134,868 B2Granted
Memory device biasing method and apparatus
AssigneeMicron Technology, Inc.
InventorUday Chandrasekhar
Life of this patent
Estimating the term…
Abstract
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device.
Claims26
A method of reading a target memory cell, comprising:
- selectively enabling a target memory cell in a string of memory cells in response to the data state of the target memory cell;
- coupling a first end of the string of memory cells to a first data line and coupling a second end of the string of memory cells to a source line;
- coupling a first end of a second string of memory cells to a second data line and coupling a second end of the second string of memory cells to the source line;
- enabling remaining memory cells of the string of memory cells;
- coupling the second data line to the source line;
- and
- reading the target memory cell.
4 more elements
A method of operating an array of memory cells, comprising:
- coupling a first data line to a first end of a string of memory cells;
- coupling a second end of the string of memory cells to a source line;
- coupling a second data line to a first end of a second string of memory cells;
- coupling a second end of the second string of memory cells to the source line;
- coupling the second data line to the source line;
- and
- sensing a target memory cell of the string of memory cells.
4 more elements
A method of sensing in an array of memory cells, comprising:
- coupling a first plurality of alternating data lines to a source line;
- coupling a first plurality of strings of memory cells to the first plurality of alternating data lines;
- coupling a second plurality of strings of memory cells to a second plurality of alternating data lines, wherein the second plurality of alternating data lines are different than the first plurality of alternating data lines and wherein the second plurality of strings of memory cells are different than the first plurality of strings of memory cells;
- coupling the second plurality of strings of memory cells to the source line;
- and
- sensing a selected memory cell of each string of the second plurality of strings of memory cells.
3 more elements
A memory device, comprising:
- at least one select gate configured to selectively couple a respective data line to a source line;
- a plurality of memory cells arranged in logical rows and columns, each row of memory cells coupled to a respective access line, each column of memory cells selectively coupled at a first end of each column to the respective data line and each column selectively coupled at, a second end to the source line;
- and
- control circuitry wherein the control circuitry is, configured to selectively enable one or more of the select gates, selectively bias each data line and selectively bias each access, line to one of a plurality of bias levels;
- wherein the at least one select gate is configured to selectively couple its respective data line to the source line regardless of activation of any memory, cell of the plurality of memory cells.
2 more elements
A memory device, comprising:
- an array of memory cells arranged in logical rows and columns;
- a first data line selectively coupled to a first end of a first column of memory cells wherein the first data line is coupled to at least one first select gate configured to selectively couple the first data line to a source line regardless of activation of any memory cell selectively coupled to the first data line;
- a second data line selectively coupled to a first end of a second column of memory cells wherein the second data line is coupled to at least one second select gate configured to selectively couple the second data line to the source line regardless of activation of any memory cell selectively coupled to the second data line;
- a plurality of access lines, each access line coupled to a respective row of memory cells;
- and
- control circuitry, wherein the control circuitry is configured to, selectively enable the at least one first select, gate and/or the at least one second select gate;
- wherein a second end of the first column of memory cells and a second end of the second column of memory cells are each selectively coupled to the source line.
4 more elements
Dependencies are inferred from the claim text.