Phase change memory devices and systems, and related programming methods
AssigneeSamsung Electronics Co., Ltd.
InventorsJun-Soo Bae, Kwang-Jin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Hye-Jin Kim
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Abstract
A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.
Claims20
A method of performing a program operation in a phase change memory device comprising a plurality of phase change memory cells, the method comprising:
- receiving program data to be programmed in selected memory cells among the plurality of phase change memory cells;
- generating bias voltages based on reference cells;
- sensing read data stored in the selected memory cells by supplying the selected memory cells with verification currents each determined by the bias voltages;
- determining whether the read data is identical to the program data;
- and
- upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.
A memory device comprising:
- a memory array comprising a plurality of phase change memory cells configured to store write data;
- and
- a generator configured to generate a level-controlled write current based on first reference cells and apply the level-controlled write current to the memory array,
- wherein the level-controlled write current is adjusted with each iterative application of the level-controlled write current, until a resistive state of the selected phase change memory cell falls within a defined resistance distribution corresponding to the write data.
A memory device comprising:
- an array of phase change memory cells divided into a first memory block including a first selected memory cell and a second memory block including a second selected memory cell;
- a bias voltage generator circuit configured to generate bias voltages in relation to respective resistance states for a plurality of reference cells;
- and
- sensing and writing circuitry configured to simultaneously write data to the first and second selected memory cells by iteratively applying a level-controlled write current to the first and second selected memory cells based, at least in part on the generated bias voltages and thereafter perform a verify-read operation on the first and second selected memory cells until respective programmed states for the first and second memory cells are equal to the write data, wherein the sensing and writing circuitry are further configured to supply the first and second selected memory cells with verification currents based on the at least one of the bias voltages during each read-verify operation.
A method of writing data to a memory comprising a plurality phase change memory cells each storing N-bit data according to respectively corresponding N2 resistance distributions, the method comprising:
- receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells;
- applying a write current to the selected phase change memory cell, wherein the write current is defined in relation to the write data;
- after applying the write current, sensing a resistive state of the selected phase change memory cell;
- comparing the sensed resistive state of the selected phase change memory cell to a reference defined in relation to the write data;
- and
- if the sensed resistive state fails comparison with the reference, adjusting the write current, and applying the adjusted write current to the selected phase change memory cell,
- the write current being generated based on reference cells formed identically to the phase change memory cells.
Dependencies are inferred from the claim text.