Semiconductor memory device and semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTakayuki Ikeda, Yoshiyuki Kurokawa
Life of this patent
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Abstract
An object is to provide a semiconductor memory device which holds data of an SRAM or a flip-flop circuit and holds data in the SRAM while electric power is not supplied from a reader or electric power is not enough, without changing a battery for driving a power supply corresponding to deterioration of the battery with time, and a semiconductor device provided with the semiconductor memory device. An SRAM cell, a decoder connected to the SRAM cell through a word line, a read/write circuit connected to the SRAM cell through the data line, and a power storage unit connected to the SRAM cell are provided. The power storage unit is charged when data is written to or read from the SRAM cell through the data line.
Claims14
A semiconductor memory device comprising:
- an SRAM cell including a first transistor, a second transistor, a first CMOS circuit and a second CMOS circuit, wherein the first CMOS circuit includes a third transistor and a fourth transistor, and wherein the second CMOS circuit includes a fifth transistor and a sixth transistor;
- a decoder connected to the SRAM cell through a word line;
- a read/write circuit connected to the SRAM cell through a first data line and a second data line;
- and
- a power storage unit connected to the SRAM cell a source or a drain of the sixth transistor,
- wherein the power storage unit stores up an electric power supplied from the first data line or the second data line through the SRAM cell.
A semiconductor device comprising:
- an antenna circuit;
- a decoder and a read/write circuit which are driven by an electric power supplied through the antenna circuit;
- an SRAM cell that is connected to the decoder through a word line and connected to the read/write circuit through a first data line and a second data line, wherein the SRAM cell includes a first transistor, a second transistor, a first CMOS circuit and a second CMOS circuit, wherein the first CMOS circuit includes a third transistor and a fourth transistor, and wherein the second CMOS circuit includes a fifth transistor and a sixth transistor;
- and
- a power storage unit that is connected to a source or a drain of the sixth transistor,
- wherein the power storage unit stores up an electric power supplied from the first data line or the second data line through the SRAM cell.
A semiconductor device comprising:
- an antenna circuit;
- a power supply portion rectifying an electric power supplied through the antenna circuit and outputting a rectified electric power;
- a decoder and a read/write circuit which are driven by an electric power supplied through the antenna circuit;
- an SRAM cell connected to the decoder through a word line and connected to the read/write circuit through a first data line and a second data line, wherein the SRAM cell includes a first transistor, a second transistor, a first CMOS circuit and a second CMOS circuit, wherein the first CMOS circuit includes a third transistor and a fourth transistor, and wherein the second CMOS circuit includes a fifth transistor and a sixth transistor;
- and
- a power storage unit connected to a source or a drain of the sixth transistor,
- wherein the power storage unit stores up an electric power supplied from the power supply portion or an electric power supplied from the first data line or the second data line through the SRAM cell.
Dependencies are inferred from the claim text.