Back to results
US 8,134,857 B2Granted
Methods for high speed reading operation of phase change memory and device employing same
AssigneeMacronix International Co., Ltd.
InventorsYuyu Lin, Yi-Chou Chen
Life of this patent
Estimating the term…
Abstract
Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.
Claims26
A method for operating a memory cell comprising a phase change memory element programmable to a plurality of resistance states, the method comprising:
- applying a first pulse across the phase change memory element to change the resistance state from a first resistance state to a second resistance state, the first pulse having leading and trailing edges with full-width at half-maximum (FWHM) points defining a first pulse width;
- and
- applying a second pulse across the phase change memory element to determine the resistance state, the second pulse having leading and trailing edges with FWHM points defining a second pulse width, the FWHM point of the second pulse leading edge and the FWHM point of the first pulse trailing edge separated by a time interval, wherein a sum of the time interval and the first pulse width is less than or equal to 70 ns, and the first pulse width is less than the time interval.
A method for operating a memory cell comprising a phase change memory element programmable to a plurality of resistance states, the method comprising:
- applying a first pulse across the phase change memory element to change the resistance state from a first resistance state to a second resistance state, the first pulse having leading and trailing edges with full-width at half-maximum (FWHM) points defining a first pulse width;
- and
- applying a second pulse across the phase change memory element to determine the resistance state, the second pulse having leading and trailing edges with FWHM points defining a second pulse width, the FWHM point of the second pulse leading edge and the FWHM point of the first pulse trailing edge separated by a time interval, wherein a sum of the time interval and the first pulse width is less than or equal to 70 ns, and the first pulse width is less than the time interval, wherein:
- the first pulse width is less than or equal to 5 ns;
- and
- the sum is less than or equal to 15 ns.
3 more elements
An integrated circuit device comprising:
- a memory cell comprising a phase change memory element programmable to a plurality of resistance states;
- a controller including logic for:
- applying a first pulse across the phase change memory element to change the resistance state from a first resistance state to a second resistance state, the first pulse having leading and trailing edges with full-width at half-maximum (FWHM) points defining a first pulse width;
- and
- applying a second pulse across the phase change memory element to determine the resistance state, the second pulse having leading and trailing edges with FWHM points defining a second pulse width, the FWHM point of the second pulse leading edge and the FWHM point of the first pulse trailing edge separated by a time interval, wherein a sum of the time interval and the first pulse width is less than or equal to 70 ns, and the first pulse width is less than the time interval.
2 more elements
An integrated circuit device comprising:
- a memory cell comprising a phase change memory element programmable to a plurality of resistance states;
- a controller including logic for:
- applying a first pulse across the phase change memory element to change the resistance state from a first resistance state to a second resistance state, the first pulse having leading and trailing edges with full-width at half-maximum (FWHM) points defining a first pulse width;
- and
- applying a second pulse across the phase change memory element to determine the resistance state, the second pulse having leading and trailing edges with FWHM points defining a second pulse width, the FWHM point of the second pulse leading edge and the FWHM point of the first pulse trailing edge separated by a time interval, wherein a sum of the time interval and the first pulse width is less than or equal to 15 ns, and the first pulse width is less than the time interval and less than or equal to 5 ns.
2 more elements
Dependencies are inferred from the claim text.