Data protection scheme during power-up in spin transfer torque magnetoresistive random access memory
AssigneeQUALCOMM Incorporated
InventorsSei Seung Yoon, Seung H. Kang
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AssigneeQUALCOMM Incorporated
InventorsSei Seung Yoon, Seung H. Kang
Estimating the term…
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines and word lines. The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal.
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array comprising:
A method of protecting data during power-up of a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array, comprising:
An apparatus for protecting data during power-up of a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array, comprising:
A computer-readable medium including program code stored thereon for protecting data during power-up of a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array, comprising:
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array comprising:
Dependencies are inferred from the claim text.