Synchronization of a data output signal to an input clock
AssigneeUrenschi Assets Limited Liability Company
InventorChris Karabatsos
Life of this patent
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Abstract
A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2n where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.
Claims16
A method of producing an output clock signal for transmission to a device, the method comprising:
- generating, using an oscillating circuit, a first internal clock signal having a first frequency that is 2n times an input frequency of an input clock signal, where n is an integer;
- generating, using the oscillating circuit, a second internal clock signal based on the first internal clock signal, wherein the second internal clock signal has a second frequency that is substantially the same as the input frequency;
- generating, using the oscillating circuit, a first output clock signal based on the second internal clock signal by applying a first time delay to the second internal clock signal such that the first output clock signal is aligned in phase with the input clock signal, wherein the first time delay is based on a phase difference between the input clock signal and the second internal clock signal;
- and
- generating, using the oscillating circuit, a second output clock signal configured to be provided to the oscillating circuit as feedback, wherein:
- the first output clock signal is transmitted to the device;
- the second output clock signal is delayed by a second time delay equal to a transmission delay associated with transmitting the first output clock signal from an output of the oscillating circuit to an input of the device;
- the first output clock signal is generated based on the second output clock signal;
- the phase of the generated first output clock signal is shifted by a time substantially equal to the transmission delay;
- and
- the first output clock signal is substantially in phase with the input clock signal when received at the input of the device.
A system for producing an output clock signal for transmission to a device, the system comprising:
- an oscillating circuit configured to:
- generate a first internal clock signal at a first frequency that is 2n times a frequency of the input clock signal, where n is an integer;
- generate a plurality of internal clock signals based on the first internal clock signal, wherein each of the plurality of internal clock signals has a frequency that is substantially the same as the input frequency;
- select a second internal clock signal from among the plurality of internal clock signals;
- and
- generate the output clock signal based on the second internal clock signal by applying a time delay to the second internal clock signal such that the output clock signal is aligned in phase with the input clock signal, wherein the time delay is based on a phase difference between the input clock signal and the second internal clock signal.
A method of producing an output clock signal for transmission to a device, the method comprising:
- generating a first internal clock signal having a first frequency that is 2n times an input frequency of an input clock signal, where n is an integer;
- generating a plurality of additional internal clock signals based on the first internal clock signal, wherein each of the plurality of internal clock signals has substantially the same frequency as the input clock signal;
- selecting a second internal clock signal from among the plurality of additional internal clock signals;
- and
- generating the output clock signal based on the second internal clock signal by applying a time delay to the second internal clock signal such that the output clock signal is aligned in phase with the input clock signal, wherein the time delay is based on a phase difference between the input clock signal and the second internal clock signal.
Dependencies are inferred from the claim text.