Computation spreading utilizing dithering for spur reduction in a digital phase lock loop

A method of reducing the generation of frequency spurs in a software based digital phase locked loop normally performed within a reference clock period, said method comprising the steps of:

• dividing computation of said phase locked loop operation into a plurality of atomic operation computations for execution in a software loop;
• dithering the duration of each iteration of said software loop;
• and
• wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock.

A method of reducing the generation of frequency spurs in a software based digital phase locked loop normally performed within a reference clock period, said method comprising the steps of:

• dividing computation of said phase locked loop operation into a plurality of atomic operation computations for execution in a software loop;
• dithering the duration of each iteration of said software loop by inserting a plurality of random wait periods throughout said software loop;
• and
• wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock.

A method of reducing the generation of frequency spurs in a software based digital phase locked loop normally performed within a reference clock period, said method comprising the steps of:

• dividing computation of said phase locked loop operation into a plurality of atomic operation computations for execution in a software loop;
• randomly shuffling the order of execution of one or more atomic operations in each iteration of said software loop;
• and
• wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock.

A phase locked loop (PLL) having a reference clock, said PLL comprising:

• means for partitioning computation of said phase locked loop into a plurality of atomic operation computations for execution in a software loop;
• means for randomizing the execution of one or more atomic operations in each iteration of said software loop;
• a processor clock having a frequency significantly higher than that of said reference clock;
• an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto;
• and
• a processor operative to generate said tuning command, said processor clocked at said processor clock rate, said processor comprising a calculation unit operative to execute instructions, wherein each instruction is operative to perform one of said atomic operation computations.