Systems and methods for minimizing static leakage of an integrated circuit
AssigneeMosaid Technologies Incorporated
InventorsRandy J. Caplan, Steven J. Schwake
Life of this patent
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Abstract
A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.
Claims23
An integrated circuit comprising:
- a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;
- a voltage generator configured to generate a negative voltage to be applied to the sleep transistor;
- and
- controller circuitry configured to:
- i) monitor drain-source current of the sleep transistor;
- ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit;
- and
- iii) adjust the negative voltage depending on the determination.
An integrated circuit comprising:
- a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;
- a voltage generator configured to generate a negative voltage to be applied to the sleep transistor;
- and
- controller circuitry configured to:
- i) monitor a drain-source current and a drain-gate current of either the sleep transistor or an emulated sleep transistor;
- ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit;
- and
- iii) adjust the negative voltage depending on the determination.
An integrated circuit comprising:
- a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;
- a voltage generator configured to generate a negative voltage to be applied to the sleep transistor;
- and
- controller circuitry configured to:
- i) induce a current through an emulated sleep transistor in proportion to a static leakage of the integrated circuit;
- ii) make a determination of whether to adjust the negative voltage depending on the amount of the current;
- and
- iii) adjust the negative voltage depending on the determination.
An integrated circuit comprising:
- a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;
- a voltage generator configured to generate a negative voltage to be applied to the sleep transistor;
- and
- a controller configured to receive the negative voltage and determine whether to adjust the negative voltage based on a comparison of a first current and a second current, the controller including:
- i) a first transistor configured to receive the negative voltage that defines the first current through the first transistor;
- ii) a second transistor configured to receive the negative voltage plus an offset voltage that define the second current through the second transistor;
- and
- iii) circuitry configured to compare the first current to the second current.
Dependencies are inferred from the claim text.