Systems and methods of low offset switched capacitor comparators

A system comprising:

• a clocked comparator with a switched capacitor input stage;
• a clocked amplifier with differential outputs electrically connected between the switched capacitor input stage and inputs to the clocked comparator;
• and
• a switch electrically connected across the differential outputs of the clocked amplifier and across the inputs to the clocked comparator, the switch configured to short the inputs of the clocked comparator during a settling period of the switched capacitor input stage,
• wherein the clocked amplifier is configured to sample an input voltage and during a sample phase, the switch configured to be open during the sample phase.

A method comprising:

• sampling a first input of a differential input voltage with a plurality of switched input capacitors and a clocked amplifier with differential outputs;
• sampling a reference voltage with the clocked amplifier;
• sampling a second input of the differential input voltage with the clocked amplifier to generate the differential input voltage;
• shorting the differential outputs of the clocked amplifier during a settling period of the plurality of switched input capacitors;
• releasing the differential outputs of the clocked amplifier to develop an amplified differential that indicates a state of a relationship of the sampled differential input voltage with respect to the sampled reference voltage;
• comparing an output voltage of the clocked amplifier with a clocked comparator to produce an indication of an outcome;
• and
• transmitting the indication of the outcome of the comparing step.

A system, comprising:

• a network of switches;
• a network of capacitors electrically connected to the network of switches, the network of capacitors and network of switches configured to sample an input voltage;
• a clocked amplifier electrically connected to the network of capacitors, the clocked amplifier having differential outputs configured to sample the input voltage applied to the network of capacitors;
• a clocked comparator electrically connected to the clocked amplifier, the clocked comparator having inputs configured to compare the differential outputs of the clocked amplifier;
• and
• a shorting switch electrically connected across the differential outputs of the clocked amplifier and across the inputs of the clocked comparator, the shorting switch configured to short the inputs of the clocked comparator during a settling period of the network of capacitors, wherein the switched capacitors are comprise a switched capacitor input stage,
• wherein the clocked amplifier is further configured to sample an input voltage and during a sample phase, the shorting switch is configured to be open during the sample phase,
• wherein the shorting switch is configured to close during a comparison phase;
• and
• wherein inputs of the clocked amplifier are configured to be shorted to outputs of the clocked amplifier during a first clock phase.