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US 8,134,398 B2Granted
Device having gate with two buried portions with different widths
AssigneeElpida Memory, Inc.
InventorTomohiro Kadoya
Life of this patent
Estimating the term…
Abstract
A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.
Claims17
A semiconductor device comprising:
- a semiconductor substrate;
- a semiconductor portion on the semiconductor substrate;
- an array of semiconductor regions on the semiconductor substrate, the array of semiconductor regions including a first semiconductor region extending in a first direction and a plurality of second semiconductor regions extending in the first direction, the first semiconductor region and the second semiconductor regions being periodically arranged in a second direction, the first semiconductor region being located at the shortest distance from the semiconductor portion in the second direction;
- a first isolation region formed between the semiconductor portion and the first semiconductor region;
- second isolation regions formed between the adjacent first and second semiconductor regions and between the adjacent second semiconductor regions, the second isolation regions being narrower than the first isolation region in the second direction;
- a liner film formed on an inner wall of trench making up each of the first and the second isolation regions;
- a dense film formed on the liner film in the trench making up each of the first and the second isolation regions;
- a gate electrode extending in the second direction, the gate electrode including buried portions buried in the first semiconductor region and each of the second semiconductor regions, and an extending portion coupling the buried portions together;
- a gate insulating film formed between the buried portion of the gate electrode and the semiconductor substrate at the second semiconductor region;
- and
- a source region and a drain region of a field effect transistor, the source and drain regions being formed in the second semiconductor region on both sides sandwiching the buried portion of the gate electrode in the first direction,
- wherein the buried portion of the gate electrode in the first semiconductor region is narrower than the buried portion of the gate electrode in the second semiconductor region in the second direction.
9 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an array of semiconductor regions on the semiconductor substrate, the array of semiconductor regions including a first semiconductor region extending in a first direction and a plurality of second semiconductor regions extending in the first direction, the first semiconductor region and the second semiconductor regions being arranged in a second direction, the first semiconductor region making up a semiconductor region located at least at one end of the array in the second direction;
- a gate electrode extending in the second direction, the gate electrode including buried portions buried in the first semiconductor region and each of the second semiconductor regions, and an extending portion coupling the buried portions together;
- a gate insulating film formed in contact with the buried portion of the gate electrode buried in the second semiconductor region;
- and
- a source region and a drain region of a field effect transistor, the source and drain regions being formed in the second semiconductor region on both sides sandwiching the buried portion of the gate electrode in the first direction,
- wherein the buried portion of the gate electrode in the first semiconductor region is narrower than the buried portion of the gate electrode in the second semiconductor region in the second direction.
4 more elements
A semiconductor device comprising:
- a dummy pattern including a first semiconductor region extending in a first direction;
- a second semiconductor region extending in the first direction;
- a gate electrode extending in the second direction, the gate electrode including buried portions buried in the first semiconductor region and each of the second semiconductor regions, and an extending portion coupling the buried portions together;
- and
- a field effect transistor including the gate electrode,
- wherein the dummy pattern and the field effect transistor make up an array arranged in the second direction, and
- the dummy pattern is located at least at one end of the array in the second direction, and
- the buried portion of the gate electrode in the first semiconductor region is narrower than the buried portion of the gate electrode in the second semiconductor region in the second direction.
5 more elements
Dependencies are inferred from the claim text.