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US 8,134,396 B2Granted
Dynamic element matching for delay lines
AssigneeInfineon Technologies AG
InventorsAndreas Wiesbauer, Luis Hernandez, Dietmar Straeussnigg
Life of this patent
Estimating the term…
Abstract
This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.
Claims19
A system comprising:
- a filter to receive and filter a target signal;
- a threshold detector to provide an indication signal when the filtered target signal exceeds a threshold voltage;
- a multiple output delay circuit comprising:
- a delay line circuit including a plurality of delay line modules, the delay line modules operable to receive a clock signal and including a delay line element, the delay line elements having delay variations and operable to generate delayed clock signals;
- an interchange circuit to dynamically interchange the delay line elements to minimize an effect of the delay variations on the delayed clock signals;
- and
- a sample and hold circuit to receive the indication signal and the delayed clock signals, to sample and hold the received indication signal using the delayed clock signals, and to generate an output signal by sampling the indication signal with the delayed clock signals.
4 more elements
In a system comprising an analog to digital converter, a device comprising:
- a delay circuit including a plurality of delay line elements, the delay circuit being operable to receive a clock signal, the delay line elements having delay variations and operable to generate delayed clock signals;
- an interchange circuit to dynamically rearrange the delay line elements to minimize an effect of the delay variations on the delayed clock signals;
- and
- a sample and hold circuit to receive a target signal and the delayed clock signals, to sample and hold a received target signal using the delayed clock signals, and to generate an output signal by sampling the target signal with the delayed clock signals.
1 more element
A method comprising:
- feeding a clock signal through a delay line circuit having a plurality of delay line elements with delay variations;
- generating a plurality of delayed clock signals with the delay line elements;
- dynamically interchanging the delay line elements to minimize the effect of the delay variations on the delayed clock signals;
- and
- generating a pulse width modulated signal with a sample and hold circuit using a target signal to be sampled and the delayed clock signals from the interchanged delay line elements.
2 more elements
Dependencies are inferred from the claim text.