Leakage power optimized structure

A set-reset latch circuit comprising first and second NAND gates for receiving first and second input signals and providing first and second output signals,

• wherein:
• the first NAND gate comprises:
• a first A input for receiving the first input signal,
• a first B input connected to a second NAND gate output,
• a first leakage current control input connected to a second A input of the second NAND gate, and
• a first NAND gate output for providing the first output signal, and
• the second NAND gate comprises:
• the second A input for receiving the second input signal,
• a second B input connected to the first NAND gate output,
• a second leakage current control input connected to the first A input of the first NAND gate, and
• the second NAND gate output for providing the second output signal,
• wherein leakage current through the first NAND gate is substantially reduced based on application of the second input signal to the first leakage current control input, and leakage current through the second NAND gate is substantially reduced based on application of the first input signal to the second leakage current control input.

A digital switching circuit for receiving a clock signal, a first data signal, and a second data signal, and for generating a first output signal and a second output signal based on the clock signal and the first and second data signals, the digital switching circuit comprising:

• a master input stage comprising:
• a first input NAND gate having:
• a clock input for receiving the clock signal,
• a J input for receiving the first data signal, and
• an output for providing a first node signal on a first node, and
• a second input NAND gate having:
• a clock input for receiving the clock signal,
• a K input for receiving the second data signal, and
• an output for providing a second node signal on a second node, and
• a master output stage comprising first and second output NAND gates, wherein
• the first output NAND gate includes:
• a first A input connected to the first node,
• a first B input connected to an output of the second output NAND gate,
• a first leakage current control input connected to the second node, and
• an output for providing a third node signal on a third node, and
• the second output NAND gate includes:
• a second A input connected to the second node,
• a second B input connected to the output of the first output NAND gate,
• a second leakage current control input connected to the first node, and
• the output for providing a fourth node signal on a fourth node,
• a slave input stage comprising:
• a third input NAND gate having:
• a clock input for receiving the clock signal,
• an input connected to the third node, and
• an output for providing a fifth node signal on a fifth node, and
• a fourth input NAND gate having:
• a clock input for receiving the clock signal,
• an input connected to the fourth node, and
• an output for providing a sixth node signal on a sixth node, and
• a slave output stage comprising third and fourth output NAND gates, wherein
• the third output NAND gate includes:
• a third A input connected to the fifth node,
• a third B input connected to an output of the fourth output NAND gate,
• a third leakage current control input connected to the sixth node, and
• an output for providing the first output signal, and
• the fourth output NAND gate includes:
• a fourth A input connected to the sixth node,
• a fourth B input connected to the output of the third output NAND gate,
• a fourth leakage current control input connected to the fifth node, and
• the output for providing the second output signal,
• wherein leakage current through the first output NAND gate is substantially reduced based on application of the second node signal to the first leakage current control input, leakage current through the second output NAND gate is substantially reduced based on application of the first node signal to the second leakage current control input, leakage current through the third output NAND gate is substantially reduced based on application of the sixth node signal to the third leakage current control input, and leakage current through the fourth output NAND gate is substantially reduced based on application of the fifth node signal to the fourth leakage current control input.

A digital switching circuit comprising:

• an input stage comprising:
• a first input NAND gate having:
• a clock input for receiving a clock signal,
• at least one data input for receiving a first data signal, and
• an output, and
• a second input NAND gate having:
• a clock input for receiving the clock signal,
• at least one data input for receiving a second data signal, and
• an output, and
• an output stage comprising first and second output NAND gates, wherein
• the first output NAND gate includes:
• a first A input connected to the output of the second input NAND gate,
• a first B input connected to an output of the second output NAND gate,
• a first leakage current control input connected to the output of the second input NAND gate, and
• an output, and
• the second output NAND gate includes:
• a second A input connected to the output of the first input NAND gate,
• a second B input connected to the output of the first output NAND gate,
• a second leakage current control input connected to the output of the first input NAND gate, and
• an output,
• wherein leakage current through the first output NAND gate is substantially reduced based on connection of the output of the second input NAND gate to the first leakage current control input, and leakage current through the second output NAND gate is substantially reduced based on connection of the output of the first input NAND gate to the second leakage current control input.