LSI test apparatus, LSI test method, and computer product
AssigneeFujitsu Semiconductor Limited
InventorSatoru Yoshikawa
Life of this patent
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Abstract
An LSI test apparatus includes a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list; a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers; a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list; and a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit.
Claims10
An LSI test apparatus comprising:
- a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list;
- a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers;
- a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list;
- and
- a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit.
An LSI test method comprising:
- synthesizing a test circuit and inserting the test circuit in a pre-test-synthesis net list;
- generating, based on a post-test-synthesis net list acquired at synthesizing, a test pattern that simultaneously activates selected gated clock buffers;
- simulating, using the test pattern generated at the generating, operation of a circuit created from the post-test-synthesis net list;
- and
- analyzing voltage drop in terms of amount, based on operation rate information acquired at the simulating.
A computer-readable recording medium storing therein an LSI test program that causes a computer to execute:
- synthesizing a test circuit and inserting the test circuit in a pre-test-synthesis net list;
- generating, based on a post-test-synthesis net list acquired at synthesizing, a test pattern that simultaneously activates selected gated clock buffers;
- simulating, using the test pattern generated at the generating, operation of a circuit created from the post-test-synthesis net list;
- and
- analyzing voltage drop in terms of amount, based on operation rate information acquired at the simulating.
Dependencies are inferred from the claim text.