US 8,134,382 B2 · Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die

Abstract

A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.

Claims19

Dependent claims

A semiconductor wafer, comprising:

a plurality of integrated circuit (IC) die areas for accommodating IC die that implement a circuit function comprising at least a first subcircuit that includes at least one matched component portion comprising at least two matched devices, wherein said first subcircuit is arranged in a layout on said IC die;
a plurality of scribe line areas having a scribe line width dimension interposed between said plurality of IC die areas, and
at least one subcircuit-based test module (TM) positioned within respective ones of said plurality of scribe line areas, said subcircuit-based TM implementing a schematic for said first subcircuit with a TM layout that copies said layout on said IC die for at least said two matched devices in said matched component portion and alters said layout on said IC die for a portion of said first subcircuit other than said two matched devices to fit said TM layout of said first subcircuit within said scribe line width dimension.

A method of designing a subcircuit-based scribe line test module (TM) for a semiconductor wafer having a plurality of integrated circuit (IC) die areas for accommodating IC die that implement a circuit function comprising at least a first subcircuit that includes at least one matched component portion comprising at least two matched devices, wherein said first subcircuit is arranged in a layout on said IC die and said semiconductor wafer includes a plurality of scribe line areas having a scribe line width dimension interposed between said plurality of IC die areas, comprising:

identifying a plurality of process sensitive subcircuits from said plurality of subcircuits, wherein said plurality of process sensitive subcircuits include said first subcircuit, each of said plurality of process sensitive subcircuits have a layout;
rank ordering said process sensitive subcircuits based on relative degrees of parametric sensitivity to process variations to generate a rank ordered list using a statistical simulation tool;
selecting at least said first subcircuit from said rank ordered list for placement within said scribe line areas, and
generating a TM layout for said first subcircuit to provide a subcircuit-based TM, wherein said TM layout of said first subcircuit implements a schematic for said first subcircuit on said IC die, copies said layout on said IC die for at least said two matched devices in said matched component portion and alters said layout on said IC die for a portion of said first subcircuit other than said two matched devices in said matched component portion to fit said TM layout of said first subcircuit within said scribe line width dimension.

1 more element

A method of a testing semiconductor wafer having a plurality of integrated circuit (IC) die areas for accommodating IC die that implement a circuit function comprising at least a first subcircuit that includes at least one matched component portion comprising at least two matched devices, wherein said first subcircuit is arranged in a layout on said IC die, said semiconductor wafer including a plurality of scribe line areas having a scribe line width dimension interposed between said plurality of IC die areas, and a subcircuit-based scribe line test module (TM) within a portion of said scribe line areas, wherein said subcircuit-based TM implements a schematic for said first subcircuit with a TM layout that copies said layout on said IC die for at least said two matched devices in said matched component portion and alters said layout on said IC die for a portion of said first subcircuit other than said matched component portion to fit said TM layout of said first subcircuit within said scribe line width dimension;

probing said subcircuit-based TMs to obtain test data, and
dispositioning said plurality of IC die on said semiconductor wafer based at least in part on said test data obtained from said subcircuit-based TMs.

Dependencies are inferred from the claim text.

Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die

Life of this patent

Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die

Life of this patent

Abstract

Claims19