Test probe structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYung Hsin Kuo
Life of this patent
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Abstract
The present disclosure provides a method for testing an integrated circuit having a load impedance. The method includes generating a first test signal having a first frequency and a second test signal having a second frequency, wherein the second frequency is greater than the first frequency, transmitting the first test signal to a substrate having a board circuit operable to process the first signal, transmitting the second test signal to a substrate, wherein the substrate includes an impedance matching circuit operable to transform the load impedance of the integrated circuit into a desired impedance for the second frequency, and sending the first and second test signals to the integrated circuit via the substrate.
Claims18
A method for testing an integrated circuit having a load impedance, comprising:
- generating a first test signal having a first frequency and a second test signal having a second frequency, wherein the second frequency is greater than the first frequency;
- providing the first test signal to a first substrate, the first substrate having a circuit operable to process the first test signal;
- providing the second test signal to a second substrate having an impedance matching circuit, the impedance matching circuit being operable to transform the load impedance into a desired impedance for the second frequency, wherein the providing of the second test signal to the second substrate includes bypassing the second test signal from the first substrate and routing the second test signal through the impedance matching circuit;
- and
- sending the first and second test signals to the integrated circuit via the second substrate.
An apparatus for testing an integrated circuit having a load impedance and a plurality of pins separated by a first pitch, comprising:
- a first substrate operable to process a first test signal having a first frequency;
- a second substrate coupled to the first substrate, the second substrate being operable to process a second test signal having a second frequency, wherein the first frequency does not exceed the second frequency, wherein the second substrate includes a first coupling mechanism operable to route the second test signal, wherein the second test signal bypasses the first substrate before being routed by the coupling mechanism;
- and
- an impedance matching circuit located on the second substrate, wherein the impedance matching circuit is operable to transform the load impedance into a desired impedance for the second frequency.
A system for testing an integrated circuit having a load impedance and a plurality of pins separated by a first pitch, comprising:
- a tester having a source impedance and operable to generate a first test signal having a first frequency and a second test signal having a second frequency for testing the integrated circuit, wherein the second frequency is greater than the first frequency;
- a first substrate coupled to the tester and operable to process the first test signal;
- a second substrate coupled to the first substrate and operable to process the second test signal, wherein the second substrate includes an impedance matching circuit operable to transform the load impedance into a desired impedance for the second frequency, wherein the second substrate includes a coupling mechanism operable to route the second test signal, wherein the second test signal bypasses the first substrate before being routed by the coupling mechanism;
- and
- a probe head having a plurality of probe sensors operable to transmit and receive the first and second test signals, wherein the probe sensors couple the second substrate to the integrated circuit.
Dependencies are inferred from the claim text.